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Searched refs:NewMIs (Results 1 – 25 of 33) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.cpp335 SmallVectorImpl<MachineInstr*> &NewMIs) const{ in StoreRegToStackSlot()
339 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
347 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); in StoreRegToStackSlot()
348 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
355 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) in StoreRegToStackSlot()
363 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); in StoreRegToStackSlot()
364 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) in StoreRegToStackSlot()
370 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) in StoreRegToStackSlot()
375 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) in StoreRegToStackSlot()
383 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) in StoreRegToStackSlot()
[all …]
DPPCInstrInfo.h74 SmallVectorImpl<MachineInstr*> &NewMIs) const;
78 SmallVectorImpl<MachineInstr*> &NewMIs) const;
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp960 SmallVectorImpl<MachineInstr*> &NewMIs, in StoreRegToStackSlot() argument
968 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
974 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) in StoreRegToStackSlot()
979 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) in StoreRegToStackSlot()
984 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) in StoreRegToStackSlot()
989 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) in StoreRegToStackSlot()
995 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT)) in StoreRegToStackSlot()
1001 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) in StoreRegToStackSlot()
1007 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X)) in StoreRegToStackSlot()
1013 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX)) in StoreRegToStackSlot()
[all …]
DPPCInstrInfo.h74 SmallVectorImpl<MachineInstr*> &NewMIs,
79 SmallVectorImpl<MachineInstr *> &NewMIs,
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTwoAddressInstructionPass.cpp957 SmallVector<MachineInstr *, 2> NewMIs; in TryInstructionTransform() local
960 NewMIs)) { in TryInstructionTransform()
964 assert(NewMIs.size() == 2 && in TryInstructionTransform()
967 NewMIs[1]->addRegisterKilled(Reg, TRI); in TryInstructionTransform()
971 mbbi->insert(mi, NewMIs[0]); in TryInstructionTransform()
972 mbbi->insert(mi, NewMIs[1]); in TryInstructionTransform()
974 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] in TryInstructionTransform()
975 << "2addr: NEW INST: " << *NewMIs[1]); in TryInstructionTransform()
978 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in TryInstructionTransform()
979 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in TryInstructionTransform()
[all …]
DMachineLICM.cpp1114 SmallVector<MachineInstr *, 2> NewMIs; in ExtractHoistableLoad() local
1118 NewMIs); in ExtractHoistableLoad()
1123 assert(NewMIs.size() == 2 && in ExtractHoistableLoad()
1126 MBB->insert(MI, NewMIs[0]); in ExtractHoistableLoad()
1127 MBB->insert(MI, NewMIs[1]); in ExtractHoistableLoad()
1130 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { in ExtractHoistableLoad()
1131 NewMIs[0]->eraseFromParent(); in ExtractHoistableLoad()
1132 NewMIs[1]->eraseFromParent(); in ExtractHoistableLoad()
1137 UpdateRegPressure(NewMIs[1]); in ExtractHoistableLoad()
1141 return NewMIs[0]; in ExtractHoistableLoad()
DVirtRegRewriter.cpp1323 SmallVector<MachineInstr*, 4> NewMIs; in OptimizeByUnfold2() local
1324 if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs)) in OptimizeByUnfold2()
1326 assert(NewMIs.size() == 1); in OptimizeByUnfold2()
1327 AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI); in OptimizeByUnfold2()
1328 VRM->transferRestorePts(&MI, NewMIs[0]); in OptimizeByUnfold2()
1329 MII = MBB->insert(MII, NewMIs[0]); in OptimizeByUnfold2()
1338 NewMIs.clear(); in OptimizeByUnfold2()
1339 if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs)) in OptimizeByUnfold2()
1341 assert(NewMIs.size() == 1); in OptimizeByUnfold2()
1342 AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI); in OptimizeByUnfold2()
[all …]
DStackSlotColoring.cpp647 SmallVector<MachineInstr*, 4> NewMIs; in UnfoldAndRewriteInstruction() local
648 bool Success = TII->unfoldMemoryOperand(MF, MI, Reg, false, false, NewMIs); in UnfoldAndRewriteInstruction()
651 MachineInstr *NewMI = NewMIs[0]; in UnfoldAndRewriteInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp1360 SmallVector<MachineInstr *, 2> NewMIs; in tryInstructionTransform() local
1363 /*UnfoldStore=*/false, NewMIs)) { in tryInstructionTransform()
1367 assert(NewMIs.size() == 2 && in tryInstructionTransform()
1370 NewMIs[1]->addRegisterKilled(Reg, TRI); in tryInstructionTransform()
1374 MBB->insert(mi, NewMIs[0]); in tryInstructionTransform()
1375 MBB->insert(mi, NewMIs[1]); in tryInstructionTransform()
1377 LLVM_DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] in tryInstructionTransform()
1378 << "2addr: NEW INST: " << *NewMIs[1]); in tryInstructionTransform()
1381 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
1382 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in tryInstructionTransform()
[all …]
DMachineLICM.cpp1308 SmallVector<MachineInstr *, 2> NewMIs; in ExtractHoistableLoad() local
1311 /*UnfoldStore=*/false, NewMIs); in ExtractHoistableLoad()
1316 assert(NewMIs.size() == 2 && in ExtractHoistableLoad()
1320 MBB->insert(Pos, NewMIs[0]); in ExtractHoistableLoad()
1321 MBB->insert(Pos, NewMIs[1]); in ExtractHoistableLoad()
1324 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { in ExtractHoistableLoad()
1325 NewMIs[0]->eraseFromParent(); in ExtractHoistableLoad()
1326 NewMIs[1]->eraseFromParent(); in ExtractHoistableLoad()
1331 UpdateRegPressure(NewMIs[1]); in ExtractHoistableLoad()
1335 return NewMIs[0]; in ExtractHoistableLoad()
/external/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp1305 SmallVector<MachineInstr *, 2> NewMIs; in tryInstructionTransform() local
1308 /*UnfoldStore=*/false, NewMIs)) { in tryInstructionTransform()
1312 assert(NewMIs.size() == 2 && in tryInstructionTransform()
1315 NewMIs[1]->addRegisterKilled(Reg, TRI); in tryInstructionTransform()
1319 MBB->insert(mi, NewMIs[0]); in tryInstructionTransform()
1320 MBB->insert(mi, NewMIs[1]); in tryInstructionTransform()
1322 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] in tryInstructionTransform()
1323 << "2addr: NEW INST: " << *NewMIs[1]); in tryInstructionTransform()
1326 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
1327 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in tryInstructionTransform()
[all …]
DMachineLICM.cpp1178 SmallVector<MachineInstr *, 2> NewMIs; in ExtractHoistableLoad() local
1181 /*UnfoldStore=*/false, NewMIs); in ExtractHoistableLoad()
1186 assert(NewMIs.size() == 2 && in ExtractHoistableLoad()
1190 MBB->insert(Pos, NewMIs[0]); in ExtractHoistableLoad()
1191 MBB->insert(Pos, NewMIs[1]); in ExtractHoistableLoad()
1194 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { in ExtractHoistableLoad()
1195 NewMIs[0]->eraseFromParent(); in ExtractHoistableLoad()
1196 NewMIs[1]->eraseFromParent(); in ExtractHoistableLoad()
1201 UpdateRegPressure(NewMIs[1]); in ExtractHoistableLoad()
1205 return NewMIs[0]; in ExtractHoistableLoad()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinInstrInfo.h65 SmallVectorImpl<MachineInstr*> &NewMIs) const;
76 SmallVectorImpl<MachineInstr*> &NewMIs) const;
DBlackfinInstrInfo.cpp213 SmallVectorImpl<MachineInstr*> &NewMIs) const { in storeRegToAddr()
254 SmallVectorImpl<MachineInstr*> &NewMIs) const { in loadRegFromAddr()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrInfo.h236 SmallVectorImpl<MachineInstr*> &NewMIs) const;
249 SmallVectorImpl<MachineInstr*> &NewMIs) const;
288 SmallVectorImpl<MachineInstr*> &NewMIs) const;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86CmovConversion.cpp767 SmallVector<MachineInstr *, 4> NewMIs; in convertCmovInstsToBranches() local
770 /*UnfoldStore*/ false, NewMIs); in convertCmovInstsToBranches()
776 auto *NewCMOV = NewMIs.pop_back_val(); in convertCmovInstsToBranches()
786 for (auto *NewMI : NewMIs) { in convertCmovInstsToBranches()
DX86InstrInfo.h364 SmallVectorImpl<MachineInstr *> &NewMIs) const;
376 SmallVectorImpl<MachineInstr *> &NewMIs) const;
410 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
DX86SpeculativeLoadHardening.cpp901 SmallVector<MachineInstr *, 2> NewMIs; in unfoldCallAndJumpLoads() local
906 /*UnfoldStore*/ false, NewMIs); in unfoldCallAndJumpLoads()
911 for (auto *NewMI : NewMIs) in unfoldCallAndJumpLoads()
916 for (auto *NewMI : NewMIs) { in unfoldCallAndJumpLoads()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h343 SmallVectorImpl<MachineInstr*> &NewMIs) const;
356 SmallVectorImpl<MachineInstr*> &NewMIs) const;
386 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h121 SmallVectorImpl<MachineInstr *> &NewMIs) const;
125 SmallVectorImpl<MachineInstr *> &NewMIs) const;
DPPCInstrInfo.cpp1187 SmallVectorImpl<MachineInstr *> &NewMIs) const { in StoreRegToStackSlot()
1194 NewMIs.push_back(addFrameReference( in StoreRegToStackSlot()
1216 SmallVector<MachineInstr *, 4> NewMIs; in storeRegToStackSlot() local
1227 StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs); in storeRegToStackSlot()
1229 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) in storeRegToStackSlot()
1230 MBB.insert(MI, NewMIs[i]); in storeRegToStackSlot()
1237 NewMIs.back()->addMemOperand(MF, MMO); in storeRegToStackSlot()
1243 SmallVectorImpl<MachineInstr *> &NewMIs) in LoadRegFromStackSlot()
1246 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg), in LoadRegFromStackSlot()
1268 SmallVector<MachineInstr*, 4> NewMIs; in loadRegFromStackSlot() local
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.cpp207 std::vector<MachineInstr*> NewMIs; in convertToThreeAddress() local
217 NewMIs.push_back(MemMI); in convertToThreeAddress()
218 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
230 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
231 NewMIs.push_back(MemMI); in convertToThreeAddress()
250 MachineInstr *NewMI = NewMIs[j]; in convertToThreeAddress()
263 MFI->insert(MBBI, NewMIs[1]); in convertToThreeAddress()
264 MFI->insert(MBBI, NewMIs[0]); in convertToThreeAddress()
265 return NewMIs[0]; in convertToThreeAddress()
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h760 SmallPtrSetImpl<MachineInstr *> &NewMIs,
975 SmallVectorImpl<MachineInstr *> &NewMIs) const { in unfoldMemoryOperand() argument
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h828 SmallPtrSetImpl<MachineInstr *> &NewMIs,
1076 SmallVectorImpl<MachineInstr *> &NewMIs) const { in unfoldMemoryOperand() argument
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp220 std::vector<MachineInstr*> NewMIs; in convertToThreeAddress() local
235 NewMIs.push_back(MemMI); in convertToThreeAddress()
236 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
253 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
254 NewMIs.push_back(MemMI); in convertToThreeAddress()
273 MachineInstr *NewMI = NewMIs[j]; in convertToThreeAddress()
287 MFI->insert(MBBI, NewMIs[1]); in convertToThreeAddress()
288 MFI->insert(MBBI, NewMIs[0]); in convertToThreeAddress()
289 return NewMIs[0]; in convertToThreeAddress()

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