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Searched refs:NewRC (Results 1 – 25 of 40) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineRegisterInfo.cpp57 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); in constrainRegClass() local
58 if (!NewRC || NewRC == OldRC) in constrainRegClass()
59 return NewRC; in constrainRegClass()
60 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
62 setRegClass(Reg, NewRC); in constrainRegClass()
63 return NewRC; in constrainRegClass()
70 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); in recomputeRegClass() local
73 if (NewRC == OldRC) in recomputeRegClass()
85 NewRC = TRI->getCommonSubClass(NewRC, OpRC); in recomputeRegClass()
86 if (!NewRC || NewRC == OldRC) in recomputeRegClass()
[all …]
DRegisterCoalescer.h56 const TargetRegisterClass *NewRC; variable
61 Partial(false), CrossClass(false), Flipped(false), NewRC(0) {} in CoalescerPair()
76 bool isPhys() const { return !NewRC; } in isPhys()
102 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
DCriticalAntiDepBreaker.cpp207 const TargetRegisterClass *NewRC = 0; in PrescanInstruction() local
210 NewRC = TII->getRegClass(MI->getDesc(), i, TRI); in PrescanInstruction()
214 if (!Classes[Reg] && NewRC) in PrescanInstruction()
215 Classes[Reg] = NewRC; in PrescanInstruction()
216 else if (!NewRC || Classes[Reg] != NewRC) in PrescanInstruction()
296 const TargetRegisterClass *NewRC = 0; in ScanInstruction() local
298 NewRC = TII->getRegClass(MI->getDesc(), i, TRI); in ScanInstruction()
302 if (!Classes[Reg] && NewRC) in ScanInstruction()
303 Classes[Reg] = NewRC; in ScanInstruction()
304 else if (!NewRC || Classes[Reg] != NewRC) in ScanInstruction()
DRegisterCoalescer.cpp158 const TargetRegisterClass *NewRC);
244 NewRC = 0; in setRegisters()
309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
312 if (!NewRC) in setRegisters()
314 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1105 const TargetRegisterClass *NewRC) { in isWinToJoinCrossClass() argument
1106 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC); in isWinToJoinCrossClass()
1135 if (SrcRC != NewRC && SrcSize > ThresSize) { in isWinToJoinCrossClass()
1140 if (DstRC != NewRC && DstSize > ThresSize) { in isWinToJoinCrossClass()
/external/llvm/lib/CodeGen/
DRegisterCoalescer.h57 const TargetRegisterClass *NewRC; variable
62 Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {} in CoalescerPair()
69 Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {} in CoalescerPair()
84 bool isPhys() const { return !NewRC; } in isPhys()
112 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
DMachineRegisterInfo.cpp56 const TargetRegisterClass *NewRC = in constrainRegClass() local
58 if (!NewRC || NewRC == OldRC) in constrainRegClass()
59 return NewRC; in constrainRegClass()
60 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
62 setRegClass(Reg, NewRC); in constrainRegClass()
63 return NewRC; in constrainRegClass()
70 const TargetRegisterClass *NewRC = in recomputeRegClass() local
74 if (NewRC == OldRC) in recomputeRegClass()
82 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, in recomputeRegClass()
84 if (!NewRC || NewRC == OldRC) in recomputeRegClass()
[all …]
DCriticalAntiDepBreaker.cpp176 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
179 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
183 if (!Classes[Reg] && NewRC) in PrescanInstruction()
184 Classes[Reg] = NewRC; in PrescanInstruction()
185 else if (!NewRC || Classes[Reg] != NewRC) in PrescanInstruction()
294 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
296 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
300 if (!Classes[Reg] && NewRC) in ScanInstruction()
301 Classes[Reg] = NewRC; in ScanInstruction()
302 else if (!NewRC || Classes[Reg] != NewRC) in ScanInstruction()
DRegisterCoalescer.cpp316 NewRC = nullptr; in setRegisters()
361 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
363 if (!NewRC) in setRegisters()
368 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
372 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
375 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
379 if (!NewRC) in setRegisters()
390 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
965 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
975 NewRC = CommonRC; in reMaterializeTrivialDef()
[all …]
DTailDuplicator.cpp392 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction() local
393 if (NewRC == nullptr) in duplicateInstruction()
394 NewRC = OrigRC; in duplicateInstruction()
395 unsigned NewReg = MRI->createVirtualRegister(NewRC); in duplicateInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp75 const TargetRegisterClass *NewRC = in constrainRegClass() local
77 if (!NewRC || NewRC == OldRC) in constrainRegClass()
78 return NewRC; in constrainRegClass()
79 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
81 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
82 return NewRC; in constrainRegClass()
133 const TargetRegisterClass *NewRC = in recomputeRegClass() local
137 if (NewRC == OldRC) in recomputeRegClass()
145 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, in recomputeRegClass()
147 if (!NewRC || NewRC == OldRC) in recomputeRegClass()
[all …]
DCriticalAntiDepBreaker.cpp193 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
196 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
200 if (!Classes[Reg] && NewRC) in PrescanInstruction()
201 Classes[Reg] = NewRC; in PrescanInstruction()
202 else if (!NewRC || Classes[Reg] != NewRC) in PrescanInstruction()
311 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
313 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
317 if (!Classes[Reg] && NewRC) in ScanInstruction()
318 Classes[Reg] = NewRC; in ScanInstruction()
319 else if (!NewRC || Classes[Reg] != NewRC) in ScanInstruction()
DRegisterCoalescer.h56 const TargetRegisterClass *NewRC = nullptr; variable
80 bool isPhys() const { return !NewRC; } in isPhys()
108 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
DRegisterCoalescer.cpp350 NewRC = nullptr; in setRegisters()
395 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
397 if (!NewRC) in setRegisters()
402 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
406 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
409 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
413 if (!NewRC) in setRegisters()
424 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1181 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
1191 NewRC = CommonRC; in reMaterializeTrivialDef()
[all …]
DTailDuplicator.cpp434 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction() local
435 if (NewRC == nullptr) in duplicateInstruction()
436 NewRC = OrigRC; in duplicateInstruction()
437 unsigned NewReg = MRI->createVirtualRegister(NewRC); in duplicateInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp252 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
257 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
298 if (NewRC->contains(*SI)) { in shouldCoalesce()
307 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128)) in shouldCoalesce()
DSystemZRegisterInfo.h86 const TargetRegisterClass *NewRC,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/
DCGSCCPassManager.cpp545 for (RefSCC *NewRC : llvm::reverse(make_range(std::next(NewRefSCCs.begin()), in updateCGAndAnalysisManagerForFunctionPass()
547 assert(NewRC != RC && "Should not encounter the current RefSCC further " in updateCGAndAnalysisManagerForFunctionPass()
549 UR.RCWorklist.insert(NewRC); in updateCGAndAnalysisManagerForFunctionPass()
551 << *NewRC << "\n"); in updateCGAndAnalysisManagerForFunctionPass()
DLazyCallGraph.cpp1712 RefSCC *NewRC = createRefSCC(*this); in buildRefSCCs() local
1713 buildSCCs(*NewRC, Nodes); in buildRefSCCs()
1718 RefSCCIndices.insert({NewRC, PostOrderRefSCCs.size()}).second; in buildRefSCCs()
1721 PostOrderRefSCCs.push_back(NewRC); in buildRefSCCs()
1723 NewRC->verify(); in buildRefSCCs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.h68 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
DHexagonRegisterInfo.cpp250 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
257 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
DHexagonVLIWPacketizer.h136 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h195 const TargetRegisterClass *NewRC) const override;
DARMBaseRegisterInfo.cpp788 const TargetRegisterClass *NewRC) const { in shouldCoalesce()
797 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) in shouldCoalesce()
801 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); in shouldCoalesce()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h210 const TargetRegisterClass *NewRC,
DARMBaseRegisterInfo.cpp807 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
817 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
822 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); in shouldCoalesce()

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