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Searched refs:NextOp (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DMLxExpansionPass.cpp217 unsigned NextOp = HasLane ? 5 : 4; in ExpandFPMLxInstruction() local
218 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
219 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp283 unsigned NextOp = HasLane ? 5 : 4; in ExpandFPMLxInstruction() local
284 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction()
/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp283 unsigned NextOp = HasLane ? 5 : 4; in ExpandFPMLxInstruction() local
284 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineInstr.cpp88 MachineOperand *NextOp = Contents.Reg.Next; in RemoveRegOperandFromRegInfo() local
89 *Contents.Reg.Prev = NextOp; in RemoveRegOperandFromRegInfo()
90 if (NextOp) { in RemoveRegOperandFromRegInfo()
91 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); in RemoveRegOperandFromRegInfo()
92 NextOp->Contents.Reg.Prev = Contents.Reg.Prev; in RemoveRegOperandFromRegInfo()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp11795 SDValue NextOp = N->getOperand(i); in combineElementTruncationToVectorTruncation() local
11796 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
11798 unsigned NextConversion = NextOp.getOperand(0).getOpcode(); in combineElementTruncationToVectorTruncation()
11805 if (Is32Bit && !isFPExtLoad(NextOp.getOperand(0).getOperand(0))) in combineElementTruncationToVectorTruncation()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp6261 unsigned NextOp = N0.getOpcode(); in visitRotate() local
6263 if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) { in visitRotate()
6268 bool SameSide = (N->getOpcode() == NextOp); in visitRotate()