| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 145 CCValAssign NextVA = VAs[1]; in assignCustomValue() local
146 assert(NextVA.needsCustom() && "Value doesn't need custom handling"); in assignCustomValue()
147 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type"); in assignCustomValue()
149 assert(VA.getValNo() == NextVA.getValNo() && in assignCustomValue()
153 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
164 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
374 CCValAssign NextVA = VAs[1]; in assignCustomValue() local
375 assert(NextVA.needsCustom() && "Value doesn't need custom handling"); in assignCustomValue()
376 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type"); in assignCustomValue()
378 assert(VA.getValNo() == NextVA.getValNo() && in assignCustomValue()
[all …]
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| D | ARMISelLowering.h | 618 CCValAssign &VA, CCValAssign &NextVA,
622 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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| D | ARMFastISel.cpp | 2011 CCValAssign &NextVA = ArgLocs[++i]; in ProcessCallArgs() local
2013 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2018 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
2021 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
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| D | ARMISelLowering.cpp | 1745 CCValAssign &VA, CCValAssign &NextVA, in PassF64ArgInRegs() argument
1754 if (NextVA.isRegLoc()) in PassF64ArgInRegs()
1755 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id))); in PassF64ArgInRegs()
1757 assert(NextVA.isMemLoc()); in PassF64ArgInRegs()
1763 dl, DAG, NextVA, in PassF64ArgInRegs()
3507 CCValAssign &NextVA, in GetF64FormalArgument() argument
3525 if (NextVA.isMemLoc()) { in GetF64FormalArgument()
3527 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true); in GetF64FormalArgument()
3535 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in GetF64FormalArgument()
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| /external/clang/include/clang/AST/ |
| D | StmtIterator.h | 65 void NextVA();
93 NextVA();
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| /external/clang/lib/AST/ |
| D | StmtIterator.cpp | 33 void StmtIteratorBase::NextVA() { in NextVA() function in StmtIteratorBase
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 191 CCValAssign &NextVA = ArgLocs[++i]; in LowerFormalArguments() local
194 if (NextVA.isMemLoc()) { in LowerFormalArguments()
196 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); in LowerFormalArguments()
202 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments()
481 CCValAssign &NextVA = ArgLocs[++i]; in LowerCall() local
482 if (NextVA.isRegLoc()) { in LowerCall()
483 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); in LowerCall()
486 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; in LowerCall()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 389 CCValAssign &VA, CCValAssign &NextVA,
393 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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| D | ARMFastISel.cpp | 1643 CCValAssign &NextVA = ArgLocs[++i]; in ProcessCallArgs() local
1646 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false; in ProcessCallArgs()
1650 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1653 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
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| D | ARMISelLowering.cpp | 1190 CCValAssign &VA, CCValAssign &NextVA, in PassF64ArgInRegs() argument
1199 if (NextVA.isRegLoc()) in PassF64ArgInRegs()
1200 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); in PassF64ArgInRegs()
1202 assert(NextVA.isMemLoc()); in PassF64ArgInRegs()
1207 dl, DAG, NextVA, in PassF64ArgInRegs()
2363 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, in GetF64FormalArgument() argument
2380 if (NextVA.isMemLoc()) { in GetF64FormalArgument()
2382 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); in GetF64FormalArgument()
2390 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in GetF64FormalArgument()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 511 CCValAssign &VA, CCValAssign &NextVA,
515 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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| D | ARMFastISel.cpp | 1984 CCValAssign &NextVA = ArgLocs[++i]; in ProcessCallArgs() local
1986 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
1991 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1994 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
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| D | ARMISelLowering.cpp | 1547 CCValAssign &VA, CCValAssign &NextVA, in PassF64ArgInRegs() argument
1557 if (NextVA.isRegLoc()) in PassF64ArgInRegs()
1558 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id))); in PassF64ArgInRegs()
1560 assert(NextVA.isMemLoc()); in PassF64ArgInRegs()
1566 dl, DAG, NextVA, in PassF64ArgInRegs()
3074 CCValAssign &NextVA, in GetF64FormalArgument() argument
3092 if (NextVA.isMemLoc()) { in GetF64FormalArgument()
3094 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); in GetF64FormalArgument()
3103 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in GetF64FormalArgument()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 424 CCValAssign &NextVA = ArgLocs[++i]; in LowerFormalArguments_32() local
427 if (NextVA.isMemLoc()) { in LowerFormalArguments_32()
429 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); in LowerFormalArguments_32()
435 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
877 CCValAssign &NextVA = ArgLocs[++i]; in LowerCall_32() local
878 if (NextVA.isRegLoc()) { in LowerCall_32()
879 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1)); in LowerCall_32()
882 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; in LowerCall_32()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 425 CCValAssign &NextVA = ArgLocs[++i]; in LowerFormalArguments_32() local
428 if (NextVA.isMemLoc()) { in LowerFormalArguments_32()
430 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); in LowerFormalArguments_32()
434 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
867 CCValAssign &NextVA = ArgLocs[++i]; in LowerCall_32() local
868 if (NextVA.isRegLoc()) { in LowerCall_32()
869 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1)); in LowerCall_32()
872 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; in LowerCall_32()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 2252 CCValAssign &NextVA, const X86Subtarget &Subtarget) { in Passv64i1ArgInRegs() argument
2256 assert(VA.isRegLoc() && NextVA.isRegLoc() && in Passv64i1ArgInRegs()
2271 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi)); in Passv64i1ArgInRegs()
2543 static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, in getv64i1Argument() argument
2551 assert(NextVA.getValVT() == VA.getValVT() && in getv64i1Argument()
2553 assert(VA.isRegLoc() && NextVA.isRegLoc() && in getv64i1Argument()
2569 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in getv64i1Argument()
2578 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag); in getv64i1Argument()
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