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Searched refs:O6 (Results 1 – 25 of 229) sorted by relevance

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/external/webp/src/dsp/
Dmips_macro.h51 #define MUL_SHIFT_SUM(O0, O1, O2, O3, O4, O5, O6, O7, \ argument
60 "mul %[" #O6 "], %[" #I3 "], %[kC2] \n\t" \
68 "sra %[" #O6 "], %[" #O6 "], 16 \n\t" \
97 #define SHIFT_R_SUM_X2(O0, O1, O2, O3, O4, O5, O6, O7, \ argument
105 "addq.ph %[" #O6 "], %[" #I3 "], %[" #I7 "] \n\t" \
113 "shra.ph %[" #O6 "], %[" #O6 "], 3 \n\t" \
141 #define CONVERT_2_BYTES_TO_HALF(O0, O1, O2, O3, O4, O5, O6, O7, \ argument
149 "preceu.ph.qbr %[" #O6 "], %[" #I3 "] \n\t" \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcFrameLowering.cpp52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
53 .addReg(SP::O6).addImm(NumBytes); in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
82 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
187 .addReg(SP::O6).addImm(Bias); in emitPrologue()
189 regUnbiased = SP::O6; in emitPrologue()
198 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6) in emitPrologue()
301 FrameReg = SP::O6; // %sp in getFrameIndexReference()
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DSparcRegisterInfo.td142 def O6 : Ri<14, "SP">, DwarfRegNum<[14]>;
292 def O6_O7 : Rdi<14, "O6", [O6, O7]>;
DSparcRegisterInfo.cpp71 Reserved.set(SP::O6); in getReservedRegs()
DSparcISelLowering.cpp821 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
837 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
873 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
882 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
911 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
1022 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7) in getRegisterByName()
1213 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); in LowerCall_64()
1258 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); in LowerCall_64()
1742 setStackPointerRegisterToSaveRestore(SP::O6); in SparcTargetLowering()
2647 unsigned SPReg = SP::O6; in LowerDYNAMIC_STACKALLOC()
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/external/llvm/lib/Target/Sparc/
DSparcFrameLowering.cpp52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
53 .addReg(SP::O6).addImm(NumBytes); in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
82 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
182 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1); in emitPrologue()
283 FrameReg = SP::O6; // %sp in getFrameIndexReference()
310 || !MRI.reg_nodbg_empty(SP::O6) // %SP is used in isLeafProc()
DSparcRegisterInfo.td142 def O6 : Ri<14, "SP">, DwarfRegNum<[14]>;
292 def O6_O7 : Rdi<14, "O6", [O6, O7]>;
DSparcRegisterInfo.cpp71 Reserved.set(SP::O6); in getReservedRegs()
DSparcISelLowering.cpp829 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
846 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
883 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
893 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
924 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
1036 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7) in getRegisterByName()
1228 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); in LowerCall_64()
1276 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); in LowerCall_64()
1729 setStackPointerRegisterToSaveRestore(SP::O6); in SparcTargetLowering()
2594 unsigned SPReg = SP::O6; in LowerDYNAMIC_STACKALLOC()
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcFrameLowering.cpp55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) in emitPrologue()
56 .addReg(SP::O6).addImm(NumBytes); in emitPrologue()
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) in emitPrologue()
66 .addReg(SP::O6).addReg(SP::G1); in emitPrologue()
DSparcRegisterInfo.cpp49 Reserved.set(SP::O6); in getReservedRegs()
68 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); in eliminateCallFramePseudoInstr()
DSparcRegisterInfo.td66 def O6 : Ri<14, "SP">, DwarfRegNum<[14]>;
150 O6, // stack ptr
DSparcISelLowering.cpp437 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall()
454 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall()
487 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall()
497 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall()
528 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall()
800 setStackPointerRegisterToSaveRestore(SP::O6); in SparcTargetLowering()
1060 unsigned SPReg = SP::O6; in LowerDYNAMIC_STACKALLOC()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCTargetDesc.cpp38 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); in createSparcMCAsmInfo()
47 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); in createSparcV9MCAsmInfo()
/external/ltp/testcases/kernel/syscalls/ptrace/
Dsimple_tracer.c93 #define O6 u_regs[13] in decode_regs()
108 decode(O6); in decode_regs()
/external/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCTargetDesc.cpp38 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); in createSparcMCAsmInfo()
47 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); in createSparcV9MCAsmInfo()
/external/freetype/builds/compiler/
Demx.mk64 CFLAGS ?= -c -g -O6 -Wall
/external/honggfuzz/examples/apache-httpd/corpus_http2/
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/external/honggfuzz/examples/apache-httpd/corpus_http1/
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/external/zlib/src/old/os2/
DMakefile.os215 CFLAGS=-O6 -Wall
/external/ImageMagick/PerlMagick/t/reference/write/composite/
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