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Searched refs:ODPG_DATA_CTRL_REG (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_bist.c33 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
38 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
65 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_bist_activate()
433 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in mv_ddr_bist_tx()
451 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in mv_ddr_odpg_bist_prepare()
456 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in mv_ddr_odpg_bist_prepare()
506 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in mv_ddr_dm_vw_get()
525 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
530 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
558 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, in mv_ddr_dm_vw_get()
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Dddr3_training_ip_engine.c382 ODPG_DATA_CTRL_REG, in ddr3_tip_ip_training()
391 ODPG_DATA_CTRL_REG, 0x3 | cs_num << 26, in ddr3_tip_ip_training()
561 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_ip_training()
637 ODPG_DATA_CTRL_REG, data_value, 0xaffffffc); in ddr3_tip_configure_odpg()
720 ODPG_DATA_CTRL_REG, (cs_num_type << 26), (3 << 26))); in ddr3_tip_read_training_result()
891 ODPG_DATA_CTRL_REG, reg_data, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
895 ODPG_DATA_CTRL_REG, (0x1 | (effective_cs << 26)), in ddr3_tip_load_pattern_to_mem()
920 ODPG_DATA_CTRL_REG, (u32)(0x1 << 31), in ddr3_tip_load_pattern_to_mem()
931 ODPG_DATA_CTRL_REG, (0x1 << 30), (u32) (0x3 << 30))); in ddr3_tip_load_pattern_to_mem()
936 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
Dddr3_training_leveling.c113 ODPG_DATA_CTRL_REG, 0x3, 0x3)); in ddr3_tip_dynamic_read_leveling()
221 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_read_leveling()
278 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
287 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
488 ODPG_DATA_CTRL_REG, 0x3, 0x3)); in ddr3_tip_dynamic_per_bit_read_leveling()
594 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_dynamic_per_bit_read_leveling()
758 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
766 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
1757 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG, in mv_ddr_rl_dqs_burst()
Dmv_ddr_regs.h274 #define ODPG_DATA_CTRL_REG 0x1630 macro