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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2006-2008
4  * Texas Instruments, <www.ti.com>
5  * Richard Woodruff <r-woodruff2@ti.com>
6  * Syed Mohammed Khasim <x0khasim@ti.com>
7  */
8 
9 #ifndef _OMAP3_H_
10 #define _OMAP3_H_
11 
12 #include <linux/sizes.h>
13 
14 /* Stuff on L3 Interconnect */
15 #define SMX_APE_BASE			0x68000000
16 
17 /* GPMC */
18 #define OMAP34XX_GPMC_BASE		0x6E000000
19 
20 /* SMS */
21 #define OMAP34XX_SMS_BASE		0x6C000000
22 
23 /* SDRC */
24 #define OMAP34XX_SDRC_BASE		0x6D000000
25 
26 /*
27  * L4 Peripherals - L4 Wakeup and L4 Core now
28  */
29 #define OMAP34XX_CORE_L4_IO_BASE	0x48000000
30 #define OMAP34XX_WAKEUP_L4_IO_BASE	0x48300000
31 #define OMAP34XX_ID_L4_IO_BASE		0x4830A200
32 #define OMAP34XX_L4_PER			0x49000000
33 #define OMAP34XX_L4_IO_BASE		OMAP34XX_CORE_L4_IO_BASE
34 
35 /* DMA4/SDMA */
36 #define OMAP34XX_DMA4_BASE              0x48056000
37 
38 /* CONTROL */
39 #define OMAP34XX_CTRL_BASE		(OMAP34XX_L4_IO_BASE + 0x2000)
40 
41 #ifndef __ASSEMBLY__
42 /* Signal Integrity Parameter Control Registers */
43 struct control_prog_io {
44 	unsigned char res[0x408];
45 	unsigned int io2;		/* 0x408 */
46 	unsigned char res2[0x38];
47 	unsigned int io0;		/* 0x444 */
48 	unsigned int io1;		/* 0x448 */
49 };
50 #endif /* __ASSEMBLY__ */
51 
52 /* Bit definition for CONTROL_PROG_IO1 */
53 #define PRG_I2C2_PULLUPRESX		0x00000001
54 
55 /* Scratchpad memory */
56 #define OMAP34XX_SCRATCHPAD		(OMAP34XX_CTRL_BASE + 0x910)
57 
58 /* UART */
59 #define OMAP34XX_UART1			(OMAP34XX_L4_IO_BASE + 0x6a000)
60 #define OMAP34XX_UART2			(OMAP34XX_L4_IO_BASE + 0x6c000)
61 #define OMAP34XX_UART3			(OMAP34XX_L4_PER + 0x20000)
62 #define OMAP34XX_UART4			(OMAP34XX_L4_PER + 0x42000)
63 
64 /* General Purpose Timers */
65 #define OMAP34XX_GPT1			0x48318000
66 #define OMAP34XX_GPT2			0x49032000
67 #define OMAP34XX_GPT3			0x49034000
68 #define OMAP34XX_GPT4			0x49036000
69 #define OMAP34XX_GPT5			0x49038000
70 #define OMAP34XX_GPT6			0x4903A000
71 #define OMAP34XX_GPT7			0x4903C000
72 #define OMAP34XX_GPT8			0x4903E000
73 #define OMAP34XX_GPT9			0x49040000
74 #define OMAP34XX_GPT10			0x48086000
75 #define OMAP34XX_GPT11			0x48088000
76 #define OMAP34XX_GPT12			0x48304000
77 
78 /* WatchDog Timers (1 secure, 3 GP) */
79 #define WD1_BASE			0x4830C000
80 #define WD2_BASE			0x48314000
81 #define WD3_BASE			0x49030000
82 
83 /* 32KTIMER */
84 #define SYNC_32KTIMER_BASE		0x48320000
85 
86 #ifndef __ASSEMBLY__
87 
88 struct s32ktimer {
89 	unsigned char res[0x10];
90 	unsigned int s32k_cr;		/* 0x10 */
91 };
92 
93 #define DEVICE_TYPE_SHIFT		0x8
94 #define DEVICE_TYPE_MASK		(0x7 << DEVICE_TYPE_SHIFT)
95 
96 #endif /* __ASSEMBLY__ */
97 
98 #ifndef __ASSEMBLY__
99 struct gpio {
100 	unsigned char res1[0x34];
101 	unsigned int oe;		/* 0x34 */
102 	unsigned int datain;		/* 0x38 */
103 	unsigned char res2[0x54];
104 	unsigned int cleardataout;	/* 0x90 */
105 	unsigned int setdataout;	/* 0x94 */
106 };
107 #endif /* __ASSEMBLY__ */
108 
109 #define GPIO0				(0x1 << 0)
110 #define GPIO1				(0x1 << 1)
111 #define GPIO2				(0x1 << 2)
112 #define GPIO3				(0x1 << 3)
113 #define GPIO4				(0x1 << 4)
114 #define GPIO5				(0x1 << 5)
115 #define GPIO6				(0x1 << 6)
116 #define GPIO7				(0x1 << 7)
117 #define GPIO8				(0x1 << 8)
118 #define GPIO9				(0x1 << 9)
119 #define GPIO10				(0x1 << 10)
120 #define GPIO11				(0x1 << 11)
121 #define GPIO12				(0x1 << 12)
122 #define GPIO13				(0x1 << 13)
123 #define GPIO14				(0x1 << 14)
124 #define GPIO15				(0x1 << 15)
125 #define GPIO16				(0x1 << 16)
126 #define GPIO17				(0x1 << 17)
127 #define GPIO18				(0x1 << 18)
128 #define GPIO19				(0x1 << 19)
129 #define GPIO20				(0x1 << 20)
130 #define GPIO21				(0x1 << 21)
131 #define GPIO22				(0x1 << 22)
132 #define GPIO23				(0x1 << 23)
133 #define GPIO24				(0x1 << 24)
134 #define GPIO25				(0x1 << 25)
135 #define GPIO26				(0x1 << 26)
136 #define GPIO27				(0x1 << 27)
137 #define GPIO28				(0x1 << 28)
138 #define GPIO29				(0x1 << 29)
139 #define GPIO30				(0x1 << 30)
140 #define GPIO31				(0x1 << 31)
141 
142 /* base address for indirect vectors (internal boot mode) */
143 #define SRAM_OFFSET0			0x40000000
144 #define SRAM_OFFSET1			0x00200000
145 #define SRAM_OFFSET2			0x0000F800
146 #define SRAM_VECT_CODE			(SRAM_OFFSET0 | SRAM_OFFSET1 | \
147 					 SRAM_OFFSET2)
148 #define SRAM_CLK_CODE			(SRAM_VECT_CODE + 64)
149 
150 #define NON_SECURE_SRAM_START		0x40208000 /* Works for GP & EMU */
151 #define NON_SECURE_SRAM_END		0x40210000
152 #define NON_SECURE_SRAM_IMG_END		0x4020F000
153 #define SRAM_SCRATCH_SPACE_ADDR		(NON_SECURE_SRAM_IMG_END - SZ_1K)
154 
155 #define LOW_LEVEL_SRAM_STACK		0x4020FFFC
156 
157 /* scratch area - accessible on both EMU and GP */
158 #define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	NON_SECURE_SRAM_START
159 
160 #define DEBUG_LED1			149	/* gpio */
161 #define DEBUG_LED2			150	/* gpio */
162 
163 #define XDR_POP		5	/* package on package part */
164 #define SDR_DISCRETE	4	/* 128M memory SDR module */
165 #define DDR_STACKED	3	/* stacked part on 2422 */
166 #define DDR_COMBO	2	/* combo part on cpu daughter card */
167 #define DDR_DISCRETE	1	/* 2x16 parts on daughter card */
168 
169 #define DDR_100		100	/* type found on most mem d-boards */
170 #define DDR_111		111	/* some combo parts */
171 #define DDR_133		133	/* most combo, some mem d-boards */
172 #define DDR_165		165	/* future parts */
173 
174 #define CPU_3430	0x3430
175 
176 /*
177  * 343x real hardware:
178  *  ES1     = rev 0
179  *
180  *  ES2 onwards, the value maps to contents of IDCODE register [31:28].
181  *
182  * Note : CPU_3XX_ES20 is used in cache.S.  Please review before changing.
183  */
184 #define CPU_3XX_ES10		0
185 #define CPU_3XX_ES20		1
186 #define CPU_3XX_ES21		2
187 #define CPU_3XX_ES30		3
188 #define CPU_3XX_ES31		4
189 #define CPU_3XX_ES312		7
190 #define CPU_3XX_MAX_REV		8
191 
192 /*
193  * 37xx real hardware:
194  * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
195  */
196 
197 #define CPU_37XX_ES10		0
198 #define CPU_37XX_ES11		1
199 #define CPU_37XX_ES12		2
200 #define CPU_37XX_MAX_REV	3
201 
202 #define CPU_3XX_ID_SHIFT	28
203 
204 #define WIDTH_8BIT		0x0000
205 #define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
206 
207 /*
208  * Hawkeye values
209  */
210 #define HAWKEYE_OMAP34XX	0xb7ae
211 #define HAWKEYE_AM35XX		0xb868
212 #define HAWKEYE_OMAP36XX	0xb891
213 
214 #define HAWKEYE_SHIFT		12
215 
216 /*
217  * Define CPU families
218  */
219 #define CPU_OMAP34XX		0x3400	/* OMAP34xx/OMAP35 devices */
220 #define CPU_AM35XX		0x3500	/* AM35xx devices          */
221 #define CPU_OMAP36XX		0x3600	/* OMAP36xx devices        */
222 
223 /*
224  * Control status register values corresponding to cpu variants
225  */
226 #define OMAP3503		0x5c00
227 #define OMAP3515		0x1c00
228 #define OMAP3525		0x4c00
229 #define OMAP3530		0x0c00
230 
231 #define AM3505			0x5c00
232 #define AM3517			0x1c00
233 
234 #define OMAP3730		0x0c00
235 #define OMAP3725		0x4c00
236 #define AM3715			0x1c00
237 #define AM3703			0x5c00
238 
239 #define OMAP3730_1GHZ		0x0e00
240 #define OMAP3725_1GHZ		0x4e00
241 #define AM3715_1GHZ		0x1e00
242 #define AM3703_1GHZ		0x5e00
243 
244 /*
245  * ROM code API related flags
246  */
247 #define OMAP3_GP_ROMCODE_API_L2_INVAL		1
248 #define OMAP3_GP_ROMCODE_API_WRITE_L2ACR	2
249 #define OMAP3_GP_ROMCODE_API_WRITE_ACR		3
250 
251 /*
252  * EMU device PPA HAL related flags
253  */
254 #define OMAP3_EMU_HAL_API_L2_INVAL		40
255 #define OMAP3_EMU_HAL_API_WRITE_ACR		42
256 
257 #define OMAP3_EMU_HAL_START_HAL_CRITICAL	4
258 
259 /* ABB settings */
260 #define OMAP_ABB_SETTLING_TIME		30
261 #define OMAP_ABB_CLOCK_CYCLES		8
262 
263 /* ABB tranxdone mask */
264 #define OMAP_ABB_MPU_TXDONE_MASK	(0x1 << 26)
265 
266 #define OMAP_REBOOT_REASON_OFFSET	0x04
267 
268 /* Boot parameters */
269 #ifndef __ASSEMBLY__
270 struct omap_boot_parameters {
271 	unsigned int boot_message;
272 	unsigned char boot_device;
273 	unsigned char reserved;
274 	unsigned char reset_reason;
275 	unsigned char ch_flags;
276 	unsigned int boot_device_descriptor;
277 };
278 
279 int omap_reboot_mode(char *mode, unsigned int length);
280 int omap_reboot_mode_clear(void);
281 int omap_reboot_mode_store(char *mode);
282 #endif
283 
284 #endif
285