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Searched refs:OPERAND_REGISTER (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenInstrInfo.inc3927 …= { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OP…
3928 …= { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OP…
3929 …= { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OP…
3930 static const MCOperandInfo OperandInfo11[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER …
3931 static const MCOperandInfo OperandInfo12[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER …
3932 static const MCOperandInfo OperandInfo13[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER …
3933 static const MCOperandInfo OperandInfo14[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }…
3935 …RY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, };
3936 …RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIE…
3937 …RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIE…
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenInstrInfo.inc3746 …] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::O…
3747 …0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips:…
3748 …0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips:…
3749 …0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips:…
3750 …OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GP…
3751 …OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GP…
3752 …OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GP…
3753 … MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { M…
3754 …OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GP…
3755 … MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { M…
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenInstrInfo.inc5513 …OPERAND_REGISTER, 0 }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCO…
5514 …{ AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI:…
5515 … { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::…
5516 …, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch…
5517 …, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch…
5518 … MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch…
5519 …OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << …
5520 …AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI:…
5521 … MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch…
5522 …, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch…
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenInstrInfo.inc4304 …o31[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPE…
4305 …o32[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPE…
4306 …sID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::…
4307 …o34[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPE…
4308 …o35[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPE…
4310 …o37[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPE…
4311 … 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::…
4313 …ATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPE…
4314 …OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID,…
4315 static const MCOperandInfo OperandInfo42[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 …
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenInstrInfo.inc16883 static const MCOperandInfo OperandInfo31[] = { { X86::VR256RegClassID, 0, MCOI::OPERAND_REGISTER, 0…
16884 static const MCOperandInfo OperandInfo32[] = { { X86::VR128XRegClassID, 0, MCOI::OPERAND_REGISTER, …
16885 static const MCOperandInfo OperandInfo33[] = { { X86::VR256XRegClassID, 0, MCOI::OPERAND_REGISTER, …
16886 static const MCOperandInfo OperandInfo34[] = { { X86::VR512RegClassID, 0, MCOI::OPERAND_REGISTER, 0…
16887 …[] = { { X86::VR512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::VK16WMRegClassID, 0, MCOI::O…
16888 …[] = { { X86::VR512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::VK8WMRegClassID, 0, MCOI::OP…
16889 static const MCOperandInfo OperandInfo37[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0…
16890 static const MCOperandInfo OperandInfo38[] = { { X86::FR32XRegClassID, 0, MCOI::OPERAND_REGISTER, 0…
16891 static const MCOperandInfo OperandInfo39[] = { { X86::FR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 …
16892 static const MCOperandInfo OperandInfo40[] = { { X86::FR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 …
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/
DMachineInstrTest.cpp109 {0, 0, MCOI::OPERAND_REGISTER, 0}, in TEST()
110 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}; in TEST()
178 {0, 0, MCOI::OPERAND_REGISTER, 0}, in TEST()
179 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}; in TEST()
253 MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0}; in TEST()
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h46 OPERAND_REGISTER, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/Disassembler/
DWebAssemblyDisassembler.cpp172 case MCOI::OPERAND_REGISTER: { in getInstruction()
/external/llvm/lib/Target/WebAssembly/Disassembler/
DWebAssemblyDisassembler.cpp105 case MCOI::OPERAND_REGISTER: { in getInstruction()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h47 OPERAND_REGISTER = 2, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCInstrDesc.h47 OPERAND_REGISTER = 2, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
DMCInstrDescView.cpp235 case llvm::MCOI::OperandType::OPERAND_REGISTER: { in randomize()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.cpp551 case MCOI::OPERAND_REGISTER: in printOperand()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp1675 case MCOI::OPERAND_REGISTER: in verifyInstruction()
/external/llvm/include/llvm/Target/
DTarget.td683 string OperandType = "OPERAND_REGISTER";
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTarget.td785 string OperandType = "OPERAND_REGISTER";
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp2666 case MCOI::OPERAND_REGISTER: in verifyInstruction()