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Searched refs:OPER_READ (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_bist.c39 (dir == OPER_READ) ? (ODPG_WRBUF_RD_CTRL_ENA << ODPG_WRBUF_RD_CTRL_OFFS) : in ddr3_tip_bist_activate()
142 i, OPER_READ, STRESS_NONE, in hws_ddr3_run_bist()
457 (dir == OPER_READ) ? (ODPG_WRBUF_RD_CTRL_ENA << ODPG_WRBUF_RD_CTRL_OFFS) : in mv_ddr_odpg_bist_prepare()
585 mv_ddr_tip_bist(OPER_READ, 0, pattern, 0, &result); in mv_ddr_dm_vw_get()
Dddr3_training_ip_def.h157 OPER_READ, enumerator
Dddr3_training_ip_engine.c409 reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30); in ddr3_tip_ip_training()
410 reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa; in ddr3_tip_ip_training()
454 direction == OPER_READ) { in ddr3_tip_ip_training()
475 direction == OPER_READ) { in ddr3_tip_ip_training()
482 direction == OPER_READ) { in ddr3_tip_ip_training()
1200 if (direction == OPER_READ) { in ddr3_tip_ip_training_wrapper()
Dddr3_training_centralization.c98 direction = OPER_READ; in ddr3_tip_centralization()
530 direction = OPER_READ; in ddr3_tip_special_rx()
Dddr3_training_pbs.c40 enum hws_dir dir = (pbs_mode == PBS_RX_MODE) ? OPER_READ : OPER_WRITE; in ddr3_tip_pbs()