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Searched refs:OPER_WRITE (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_bist.c46 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
48 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
49 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
131 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
467 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
507 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE, in mv_ddr_dm_vw_get()
517 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
539 …mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SING… in mv_ddr_dm_vw_get()
550 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE, in mv_ddr_dm_vw_get()
Dddr3_training_ip_engine.c399 tx_burst_size = (direction == OPER_WRITE) ? in ddr3_tip_ip_training()
401 delay_between_burst = (direction == OPER_WRITE) ? 2 : 0; in ddr3_tip_ip_training()
402 rd_mode = (direction == OPER_WRITE) ? 1 : 0; in ddr3_tip_ip_training()
461 direction == OPER_WRITE) { in ddr3_tip_ip_training()
464 direction == OPER_WRITE) { in ddr3_tip_ip_training()
479 direction == OPER_WRITE) { in ddr3_tip_ip_training()
1109 u8 cons_tap = (direction == OPER_WRITE) ? (64) : (0); in ddr3_tip_ip_training_wrapper()
1352 if ((byte_status[if_id][sybphy_id] != BYTE_NOT_DEFINED) && (direction == OPER_WRITE)) { in ddr3_tip_ip_training_wrapper()
Dddr3_training_ip_def.h156 OPER_WRITE, enumerator
Dddr3_training_centralization.c94 direction = OPER_WRITE; in ddr3_tip_centralization()
391 OPER_WRITE) { in ddr3_tip_centralization()
Dddr3_training_pbs.c40 enum hws_dir dir = (pbs_mode == PBS_RX_MODE) ? OPER_READ : OPER_WRITE; in ddr3_tip_pbs()