| /external/u-boot/cmd/ |
| D | test.c | 14 #define OP_AND 3 macro
47 {0, "-a", OP_AND, 1},
149 case OP_AND: in do_test()
151 last_binop = OP_AND; in do_test()
167 else if (last_binop == OP_AND) in do_test()
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_lowering_gm107.cpp | 243 bld.mkOp2(OP_AND , TYPE_U32, tmp0, tmp0, bld.mkImm(0xff)); in handlePFETCH()
244 bld.mkOp2(OP_AND , TYPE_U32, tmp1, tmp1, bld.mkImm(0xff)); in handlePFETCH()
258 Value *tmp = bld.mkOp2v(OP_AND, i->sType, bld.getScratch(), in handlePOPCNT()
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| D | nv50_ir_target_nvc0.cpp | 117 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
442 case OP_AND: in isModSupported()
596 case OP_AND: in getThroughput()
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| D | nv50_ir_target_gm107.cpp | 206 case OP_AND: in getLatency()
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| D | nv50_ir_target_nv50.cpp | 94 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x2 },
463 case OP_AND: in isModSupported()
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| D | nv50_ir_peephole.cpp | 426 if (insn->op == OP_AND) { in findOriginForTestWithZero()
619 case OP_AND: in expr()
1170 i->op = OP_AND; in opnd()
1185 Value *mod = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), abs, in opnd()
1264 case OP_AND: in opnd()
1348 i->op = OP_AND; in opnd()
1873 if ((logop->op == OP_AND || logop->op == OP_OR) && in handleLOGOP()
1892 operation redOp = (logop->op == OP_AND ? OP_SET_AND : in handleLOGOP()
2035 } else if (insn->op == OP_AND) { in handleCVT_EXTBF()
2156 if (isFloatType(i->sType) || !src || src->op != OP_AND) in handleNEG()
[all …]
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| D | nv50_ir_lowering_nvc0.cpp | 1408 op = OP_AND; in handleSharedATOMNVE4()
1500 op = OP_AND; in handleSharedATOM()
1752 ptr = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(511)); in loadSuInfo32()
1754 ptr = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(7)); in loadSuInfo32()
1855 s = bld.mkOp2v(OP_AND, TYPE_U32, ts, s, bld.loadImm(NULL, 0x7)); in adjustCoordinatesMS()
1931 bld.mkOp2(OP_AND, TYPE_U32, off, src[0], bld.loadImm(NULL, 0xffff)); in processSurfaceCoordsNVE4()
2243 ptr = bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(7)); in processSurfaceCoordsNVC0()
2671 bld.mkOp2v(OP_AND, TYPE_U32, bld.getSSA(), ld->getDef(0), in handleRDSV()
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| D | nv50_ir_emit_nv50.cpp | 1538 assert(i->op == OP_AND); in emitLogicOp()
1547 case OP_AND: code[1] = 0x04000000; break; in emitLogicOp()
1919 case OP_AND: in emitInstruction()
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| D | nv50_ir_lowering_nv50.cpp | 1194 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x0000ffff)); in handleRDSV()
1196 bld.mkOp2(OP_AND, TYPE_U32, def, tid, bld.mkImm(0x03ff0000)); in handleRDSV()
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| D | nv50_ir.h | 64 OP_AND, enumerator
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| D | nv50_ir_emit_gm107.cpp | 1653 case OP_AND: lop = 0; break; in emitLOP()
3337 case OP_AND: in emitInstruction()
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| D | nv50_ir_emit_gk110.cpp | 2576 case OP_AND: in emitInstruction()
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| D | nv50_ir_emit_nvc0.cpp | 2747 case OP_AND: in emitInstruction()
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| /external/apache-xml/src/main/java/org/apache/xpath/compiler/ |
| D | OpCodes.java | 103 public static final int OP_AND = 3; field in OpCodes
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| D | Compiler.java | 127 case OpCodes.OP_AND : in compile()
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| D | XPathParser.java | 839 insertOp(opPos, 2, OpCodes.OP_AND); in AndExpr()
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| /external/swiftshader/src/OpenGL/compiler/preprocessor/ |
| D | Token.h | 47 OP_AND, enumerator
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| D | ExpressionParser.y | 384 case pp::Token::OP_AND:
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| D | Tokenizer.l | 204 return pp::Token::OP_AND;
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| D | ExpressionParser.cpp | 1961 case pp::Token::OP_AND: in yylex()
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| D | Tokenizer.cpp | 1560 return pp::Token::OP_AND;
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 401 def OP_AND : Op<(op "&", $p0, $p1)>;
802 def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
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