Searched refs:OP_EX2 (Results 1 – 12 of 12) sorted by relevance
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_target_gm107.cpp | 121 case OP_EX2: in isBarrierRequired()
248 case OP_EX2: in getLatency()
275 case OP_EX2: in getReadLatency()
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| D | nv50_ir_target_nv50.cpp | 102 { OP_EX2, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0 },
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| D | nv50_ir_target_nvc0.cpp | 128 { OP_EX2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
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| D | nv50_ir_emit_nv50.cpp | 1502 assert(subOp == 6 && i->op == OP_EX2); in emitSFnOp()
1969 case OP_EX2: in emitInstruction()
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| D | nv50_ir_lowering_nv50.cpp | 1256 i->op = OP_EX2; in handlePOW()
1408 case OP_EX2: in visit()
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| D | nv50_ir.h | 87 OP_EX2, enumerator
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| D | nv50_ir_from_tgsi.cpp | 3334 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0); in handleInstruction()
3336 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0); in handleInstruction()
3346 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1); in handleInstruction()
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| D | nv50_ir_emit_gm107.cpp | 1401 case OP_EX2: mufu = 2; break; in emitMUFU()
3331 case OP_EX2: in emitInstruction()
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| D | nv50_ir_lowering_nvc0.cpp | 2768 i->op = OP_EX2; in handlePOW()
2868 case OP_EX2: in visit()
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| D | nv50_ir_peephole.cpp | 822 case OP_EX2: res.data.f32 = exp2f(imm.reg.data.f32); break; in unary()
1412 case OP_EX2: in opnd()
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| D | nv50_ir_emit_gk110.cpp | 2632 case OP_EX2: in emitInstruction()
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| D | nv50_ir_emit_nvc0.cpp | 2800 case OP_EX2: in emitInstruction()
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