/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
D | nv50_ir_build_util.cpp | 173 Instruction *insn = new_Instruction(func, OP_MOV, ty); in mkMov() 185 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(src->reg.size)); in mkMovToReg() 198 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(dst->reg.size)); in mkMovFromReg() 404 return mkOp1v(OP_MOV, TYPE_F32, dst ? dst : getScratch(), mkImm(f)); in loadImm() 410 return mkOp1v(OP_MOV, TYPE_F64, dst ? dst : getScratch(8), mkImm(d)); in loadImm() 416 return mkOp1v(OP_MOV, TYPE_U32, dst ? dst : getScratch(), mkImm(u)); in loadImm() 422 return mkOp1v(OP_MOV, TYPE_U64, dst ? dst : getScratch(8), mkImm(u)); in loadImm() 571 if (i->op == OP_MOV) { in split64BitOpPostRA() 581 case OP_MOV: srcNr = 1; break; in split64BitOpPostRA()
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D | nv50_ir_lowering_gm107.cpp | 60 bld.mkOp1(OP_MOV , TYPE_U32, src0, i->getSrc(0)); in handlePFETCH() 76 i->op = OP_MOV; in handleLOAD() 248 bld.mkOp1(OP_MOV , TYPE_U32, tmp2, i->getSrc(0)); in handlePFETCH()
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D | nv50_ir_peephole.cpp | 52 if (op == OP_MOV || op == OP_UNION) { in isNop() 103 if (mov->op != OP_MOV || mov->fixed || !mov->getSrc(0)->asLValue()) in visit() 171 if (!ld || (ld->op != OP_MOV) || in isImmdLoad() 263 if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV)) in visit() 321 } else if (insn->op == OP_MOV) { in visit() 381 if (i->op == OP_MOV || i->op == OP_CALL) in visit() 422 if (insn->op == OP_MOV) in findOriginForTestWithZero() 512 return OP_MOV; in getOp() 730 i->op = i->saturate ? OP_SAT : OP_MOV; in expr() 805 i->op = OP_MOV; in expr() [all …]
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D | nv50_ir_target_nvc0.cpp | 209 opInfo[i].pseudo = (i < OP_MOV); in initOpInfo() 640 if (a->op == OP_MOV || b->op == OP_MOV) in canDualIssue()
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D | nv50_ir_target_gm107.cpp | 213 case OP_MOV: in getLatency()
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D | nv50_ir_ra.cpp | 470 mov = new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size)); in visit() 505 new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size)); in visit() 519 new_Instruction(func, OP_MOV, typeOfSize(tmp->reg.size)); in visit() 1092 case OP_MOV: in doCoalesce() 2311 mov = new_Instruction(func, OP_MOV, typeOfSize(size)); in insertConstraintMoves() 2334 bool imm = defi->op == OP_MOV && in insertConstraintMoves() 2353 mov = new_Instruction(func, OP_MOV, typeOfSize(size)); in insertConstraintMoves()
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D | nv50_ir.h | 49 OP_MOV, // simple copy, no modifiers allowed enumerator 840 inline bool isPseudo() const { return op < OP_MOV; } in isPseudo()
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D | nv50_ir_target_nv50.cpp | 161 opInfo[i].pseudo = (i < OP_MOV); in initOpInfo()
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D | nv50_ir_emit_nv50.cpp | 399 assert(i->op == OP_MOV); in setSrcFileBits() 1110 const int s = (i->op == OP_MOV) ? 0 : 1; in emitAADD() 1859 case OP_MOV: in emitInstruction()
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D | nv50_ir_lowering_nvc0.cpp | 56 if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV) || in handleDIV() 761 if (i->op != OP_MOV && i->op != OP_PFETCH) in visit() 1342 bufq->op = OP_MOV; in handleBUFQ() 2590 i->op = OP_MOV; in handleRDSV() 2632 i->op = OP_MOV; in handleRDSV() 2783 i->op = OP_MOV; in handleEXPORT()
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D | nv50_ir_from_tgsi.cpp | 2215 mkOp1(OP_MOV, TYPE_U32, viewport, val); in storeDst() 3070 while (insn->op == OP_MOV) { in handleINTERP() 3300 mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c)); in handleInstruction() 3305 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0); in handleInstruction() 3311 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0); in handleInstruction() 3501 mkOp1(OP_MOV, TYPE_U32, dst0[0], zero); in handleInstruction()
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D | nv50_ir_lowering_nv50.cpp | 550 bld.mkOp1(OP_MOV, ty, t, q)->setPredicate(CC_NS, cond); in handleDIV() 1273 i->op = OP_MOV; in handleEXPORT()
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D | nv50_ir_emit_nvc0.cpp | 415 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2); in emitForm_A() 2680 case OP_MOV: in emitInstruction() 2965 if (i->op == OP_MOV && i->lanes != 0xf) { in getMinEncodingSize()
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D | nv50_ir.cpp | 103 if (insn && insn->op == OP_MOV) { in getImmediate()
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D | nv50_ir_emit_gk110.cpp | 2506 case OP_MOV: in emitInstruction()
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D | nv50_ir_emit_gm107.cpp | 3193 case OP_MOV: in emitInstruction()
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