Searched refs:OR0 (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | shift-and-i128-ubfe.ll | 99 ; GCN-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[SHLLO]], v[[ELT1PART]]
102 ; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[OR0]]:[[ZERO]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:…
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | shift-and-i128-ubfe.ll | 101 ; GCN-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[ELT1PART]], v[[SHLLO]]
104 ; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[OR0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+…
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| D | fmul.f16.ll | 212 ; VI-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[MUL_LO_LO]], v[[MUL_LO_HI]]
215 ; VI: buffer_store_dwordx2 v{{\[}}[[OR0]]:[[OR1]]{{\]}}
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| D | llvm.maxnum.f16.ll | 224 ; VI-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[MAX_LO_LO]], v[[MAX_LO_HI]]
227 ; VI: buffer_store_dwordx2 v{{\[}}[[OR0]]:[[OR1]]{{\]}}
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| D | llvm.minnum.f16.ll | 223 ; VI-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[MIN_LO_LO]], v[[MIN_LO_HI]]
226 ; VI: buffer_store_dwordx2 v{{\[}}[[OR0]]:[[OR1]]{{\]}}
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| /external/u-boot/arch/powerpc/cpu/mpc83xx/ |
| D | start.S | 1120 lwz r4, OR0@l(r3)
1123 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1174 lwz r4, OR0(r3)
1177 stw r4, OR0(r3)
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| /external/u-boot/arch/powerpc/cpu/mpc8xx/ |
| D | Kconfig | 95 hex "Preliminary value for OR0"
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| /external/u-boot/arch/powerpc/include/asm/ |
| D | fsl_lbc.h | 86 #define OR0 0x5004 /* Register offset to immr */ macro
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| /external/u-boot/include/ |
| D | ppc_asm.tmpl | 104 #define OR0 0x00000104
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| /external/u-boot/ |
| D | README | 3255 Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
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| /external/toolchain-utils/android_bench_suite/panorama_input/ |
| D | test_006.ppm | 1270 &!����� ���� ��� �� >#-�isA&/^CO�|��w�iT^6#,;(0# ��� ����#'B)1`OR0 "'#
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