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Searched refs:OR1 (Results 1 – 15 of 15) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
36 ; CHECK-NEXT: [[OR1:%.*]] = or <2 x i32> [[Y:%.*]], [[M]]
37 ; CHECK-NEXT: [[RET:%.*]] = and <2 x i32> [[OR]], [[OR1]]
51 ; CHECK-NEXT: [[OR1:%.*]] = or <3 x i32> [[Y:%.*]], [[M]]
52 ; CHECK-NEXT: [[RET:%.*]] = and <3 x i32> [[OR]], [[OR1]]
69 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], 65280
70 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
82 ; CHECK-NEXT: [[OR1:%.*]] = or <2 x i32> [[Y:%.*]], <i32 65280, i32 65280>
83 ; CHECK-NEXT: [[RET:%.*]] = and <2 x i32> [[OR]], [[OR1]]
[all …]
Dpr32686.ll12 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], or (i32 zext (i1 icmp ne (i32* bitcast (i8* @a to i…
13 ; CHECK-NEXT: store i32 [[OR1]], i32* @b, align 4
Ddemorgan.ll401 ; CHECK-NEXT: [[OR1:%.*]] = xor i1 [[OR1_DEMORGAN]], true
402 ; CHECK-NEXT: [[OR:%.*]] = zext i1 [[OR1]] to i32
431 ; CHECK-NEXT: [[OR1:%.*]] = xor <2 x i1> [[OR1_DEMORGAN]], <i1 true, i1 true>
432 ; CHECK-NEXT: [[OR:%.*]] = zext <2 x i1> [[OR1]] to <2 x i32>
Dand-or-not.ll507 ; CHECK-NEXT: [[OR1:%.*]] = or i64 [[NOTB]], [[A]]
509 ; CHECK-NEXT: [[AND:%.*]] = and i64 [[OR1]], [[OR2]]
528 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[NOTA]], [[B]]
530 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[OR1]], [[OR2]]
531 ; CHECK-NEXT: [[MUL1:%.*]] = mul i32 [[OR1]], [[OR2]]
Dor.ll554 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
555 ; CHECK-NEXT: ret i32 [[OR1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-or.mir41 ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY1]], [[COPY3]]
43 ; CHECK: $x1 = COPY [[OR1]](s64)
/external/u-boot/arch/powerpc/cpu/mpc8xx/
DKconfig105 hex "Preliminary value for OR1"
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfmul.f16.ll213 ; VI-DAG: v_or_b32_e32 v[[OR1:[0-9]+]], v[[MUL_HI_LO]], v[[MUL_HI_HI]]
215 ; VI: buffer_store_dwordx2 v{{\[}}[[OR0]]:[[OR1]]{{\]}}
Dllvm.maxnum.f16.ll225 ; VI-DAG: v_or_b32_e32 v[[OR1:[0-9]+]], v[[MAX_HI_LO]], v[[MAX_HI_HI]]
227 ; VI: buffer_store_dwordx2 v{{\[}}[[OR0]]:[[OR1]]{{\]}}
Dllvm.minnum.f16.ll224 ; VI-DAG: v_or_b32_e32 v[[OR1:[0-9]+]], v[[MIN_HI_LO]], v[[MIN_HI_HI]]
226 ; VI: buffer_store_dwordx2 v{{\[}}[[OR0]]:[[OR1]]{{\]}}
/external/u-boot/arch/powerpc/include/asm/
Dfsl_lbc.h87 #define OR1 0x500C macro
/external/llvm/test/CodeGen/AMDGPU/
Dshift-and-i128-ubfe.ll100 ; GCN-DAG: v_or_b32_e32 v[[OR1:[0-9]+]], 0, v[[SHLHI]]{{$}}
/external/u-boot/include/
Dppc_asm.tmpl106 #define OR1 0x0000010c
/external/llvm/test/Transforms/InstCombine/
Dor.ll557 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], %y
558 ; CHECK-NEXT: ret i32 [[OR1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimpleLoopUnswitch/
Dnontrivial-unswitch.ll2825 ; CHECK-NEXT: %[[OR1:.*]] = or i1 %[[V2]], %cond2
2826 ; CHECK-NEXT: %[[AND2:.*]] = and i1 %[[AND1]], %[[OR1]]