| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_64.c | 95 FAIL_IF(push_inst(compiler, ORIS | S(reg) | A(reg) | (tmp2 >> 16))); in load_immediate()
115 FAIL_IF(push_inst(compiler, ORIS | S(reg) | A(reg) | IMM(imm >> 16))); in load_immediate()
350 return push_inst(compiler, ORIS | S(src1) | A(dst) | compiler->imm); in emit_single_op()
355 return push_inst(compiler, ORIS | S(dst) | A(dst) | IMM(compiler->imm >> 16)); in emit_single_op()
476 FAIL_IF(push_inst(compiler, ORIS | S(reg) | A(reg) | IMM(init_value >> 16))); in emit_const()
|
| D | sljitNativePPC_32.c | 198 return push_inst(compiler, ORIS | S(src1) | A(dst) | compiler->imm); in emit_single_op()
203 return push_inst(compiler, ORIS | S(dst) | A(dst) | IMM(compiler->imm >> 16)); in emit_single_op()
|
| D | sljitNativePPC_common.c | 204 #define ORIS (HI(25)) macro
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
|
| D | PPCInstrInfo.td | 903 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1365 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 360 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
364 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
369 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
373 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
|
| D | PPCISelDAGToDAG.cpp | 4034 Op32.getMachineOpcode() == PPC::ORIS) { in PeepholePPC64ZExtGather()
4192 case PPC::ORIS: NewOpcode = PPC::ORIS8; break; in PeepholePPC64ZExt()
|
| D | PPCInstrInfo.td | 1987 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2681 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 378 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
382 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
387 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
391 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
|
| D | PPCISelDAGToDAG.cpp | 5881 Op32.getMachineOpcode() == PPC::ORIS) { in PeepholePPC64ZExtGather()
6039 case PPC::ORIS: NewOpcode = PPC::ORIS8; break; in PeepholePPC64ZExt()
|
| D | PPCInstrInfo.cpp | 3316 case PPC::ORIS: in isSignOrZeroExtended()
|
| D | PPCInstrInfo.td | 2213 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2961 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
|
| /external/v8/src/ppc/ |
| D | disasm-ppc.cc | 1303 case ORIS: { in InstructionDecode()
|
| D | constants-ppc.h | 1756 V(oris, ORIS, 0x64000000) \
|
| D | assembler-ppc.cc | 949 d_form(ORIS, src, dst, imm.immediate(), false); in oris()
|
| D | simulator-ppc.cc | 1904 case ORIS: { in ExecuteGeneric()
|
| /external/capstone/arch/PowerPC/ |
| D | PPCGenAsmWriter.inc | 773 22026U, // ORIS
2046 1U, // ORIS
3956 // ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8...
|
| D | PPCGenDisassemblerTables.inc | 621 /* 2472 */ MCD_OPC_Decode, 241, 5, 29, // Opcode: ORIS
|