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Searched refs:ORR (Results 1 – 25 of 103) sorted by relevance

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/external/arm-neon-tests/
DInitCache.s19 ORR r0, r0, #(0x1 <<12) ; enable I Cache
21 ORR r0, r0, #(0x1 <<2) ; enable D Cache
23 ORR r0, r0, #0x1 ; enable MMU
31 ORR r0, r0, #2 ; L2EN bit, enable L2 cache
33 ;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
34 ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
35 ORR r0, r0, #(0x1 << 5) ;Enables caching NEON data within the L1 data cache
43 ORR r0, r0, #(0x1 <<11) ; Enable all forms of branch prediction
/external/libxaac/decoder/armv7/
Dixheaacd_complex_ifft_p2.s29 ORR r4, r7, r6, LSL #2
32 ORR r4, r7, r6, LSL #4
36 ORR r4, r7, r6, LSL #8
189 ORR r4, r3, r4, LSL#1
192 ORR r6, r3, r6, LSL#1
195 ORR r5, r3, r5, LSL#1
198 ORR r7, r3, r7, LSL#1
207 ORR r4, r3, r4, LSL#1
210 ORR r8, r3, r8, LSL#1
213 ORR r5, r3, r5, LSL#1
[all …]
Dixheaacd_complex_fft_p2.s29 ORR r4, r7, r6, LSL #2
32 ORR r4, r7, r6, LSL #4
36 ORR r4, r7, r6, LSL #8
189 ORR r4, r3, r4, LSL#1
192 ORR r6, r3, r6, LSL#1
195 ORR r5, r3, r5, LSL#1
198 ORR r7, r3, r7, LSL#1
207 ORR r4, r3, r4, LSL#1
210 ORR r8, r3, r8, LSL#1
213 ORR r5, r3, r5, LSL#1
[all …]
Dixheaacd_mps_complex_fft_64_asm.s174 ORR r4, r3, r4, LSL#1
177 ORR r6, r3, r6, LSL#1
180 ORR r5, r3, r5, LSL#1
183 ORR r7, r3, r7, LSL#1
192 ORR r4, r3, r4, LSL#1
195 ORR r8, r3, r8, LSL#1
198 ORR r5, r3, r5, LSL#1
201 ORR r9, r3, r9, LSL#1
210 ORR r4, r3, r4, LSL#1
213 ORR r10, r3, r10, LSL#1
[all …]
Dixheaacd_calcmaxspectralline.s54 ORR R4, R4, R1
56 ORR R4, R4, R2
59 ORR R4, R4, R3
66 ORR R4, R4, R2
Dixheaacd_auto_corr.s111 ORR r5, r6, r5
113 ORR r5, r6, r5
115 ORR r5, r9, r5
116 ORR r5, r14, r5
Dixheaacd_expsubbandsamples.s59 ORR r12, r12, r1
86 ORR r12, r12, r3
89 ORR r12, r12, r3
Dixheaacd_enery_calc_per_subband.s85 ORR R6, R6, R4
/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_arm.s36 ORR R3<<6, R9, R9
37 ORR R4<<12, g, g
38 ORR R5<<18, R11, R11
114 ORR R1<<6, g, g
115 ORR R2<<12, R11, R11
116 ORR R3<<18, R12, R12
124 ORR R3, R4, R4
171 ORR R11<<6, R12, R12
172 ORR R5<<6, R14, R14
181 ORR R1<<6, R12, R12
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_calcmaxspectralline.s43 ORR V3.16B, V0.16B, V3.16B
44 ORR V3.16B, V1.16B, V3.16B
53 ORR W4, W4, W1
55 ORR W4, W4, W2
56 ORR W4, W4, W3
65 ORR W4, W4, W2
/external/libhevc/common/arm64/
Dihevc_sao_band_offset_chroma.s176 … ORR v4.8b, v4.8b , v13.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
184 … ORR v3.8b, v3.8b , v14.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
194 … ORR v2.8b, v2.8b , v15.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
203 … ORR v1.8b, v1.8b , v16.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
250 … ORR v12.8b, v12.8b , v17.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
258 … ORR v11.8b, v11.8b , v18.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
268 … ORR v10.8b, v10.8b , v19.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
278 … ORR v9.8b, v9.8b , v20.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
Dihevc_sao_band_offset_luma.s152 … ORR v4.8b, v4.8b , v25.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
160 … ORR v3.8b, v3.8b , v24.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
170 … ORR v2.8b, v2.8b , v23.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
180 … ORR v1.8b, v1.8b , v22.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dnegative-immediates.s133 ORR r0, r1, #0xFFFFFF00
135 # CHECK-DISABLED: ORR
137 ORR r0, r1, #0xFEFFFEFF
140 # CHECK-DISABLED: ORR
Dnegative-immediates-fail.s23 ORR r0, r1, #0xFFFFFF00 label
/external/llvm/test/CodeGen/AArch64/
Darm64-movi.ll4 ; Tests for MOV-immediate implemented with ORR-immediate.
93 ; Tests for ORR with MOVK.
Dbitfield-insert.ll418 ; Don't generate BFI/BFXIL if the immediate can be encoded in the ORR.
428 ; BFXIL will use the same constant as the ORR, so we don't care how the constant
441 ; as the original ORR are okay.
453 ; to the original ORR are not okay. In this case we would be replacing the
/external/pcre/dist2/src/sljit/
DsljitNativeARM_64.c110 #define ORR 0xaa000000 macro
710 return push_inst(compiler, ORR | RD(dst) | RN(TMP_ZERO) | RM(arg2)); in emit_op_imm()
731 return push_inst(compiler, (ORR ^ (1 << 31)) | RD(dst) | RN(TMP_ZERO) | RM(arg2)); in emit_op_imm()
776 FAIL_IF(push_inst(compiler, (ORR ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2))); in emit_op_imm()
927 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S0) | RN(TMP_ZERO) | RM(SLJIT_R0))); in sljit_emit_enter()
929 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S1) | RN(TMP_ZERO) | RM(SLJIT_R1))); in sljit_emit_enter()
931 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S2) | RN(TMP_ZERO) | RM(SLJIT_R2))); in sljit_emit_enter()
1096 FAIL_IF(push_inst(compiler, ORR | RD(TMP_REG1) | RN(TMP_ZERO) | RM(SLJIT_R0))); in sljit_emit_op0()
1101 FAIL_IF(push_inst(compiler, (ORR ^ inv_bits) | RD(TMP_REG1) | RN(TMP_ZERO) | RM(SLJIT_R0))); in sljit_emit_op0()
1526 return push_inst(compiler, ORR | RD(dst) | RN(TMP_ZERO) | RM(TMP_LR)); in sljit_emit_fast_enter()
[all …]
/external/vixl/test/aarch32/config/
Dcond-rd-rn-operand-rm-t32.json85 "Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
86 // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
236 "Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
Dcond-rd-rn-operand-const-a32.json42 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
Dcond-rd-rn-operand-rm-shift-rs-a32.json39 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
Dcond-rd-rn-operand-const-t32.json50 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-aliases.s25 ; ORR Rd, Rn, Rn is a MOV
195 ; ORR is mostly repeating bit sequences and cannot encode -1, so it only
/external/llvm/test/MC/AArch64/
Darm64-aliases.s25 ; ORR Rd, Rn, Rn is a MOV
195 ; ORR is mostly repeating bit sequences and cannot encode -1, so it only
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dbitfield-insert.ll418 ; Don't generate BFI/BFXIL if the immediate can be encoded in the ORR.
428 ; BFXIL will use the same constant as the ORR, so we don't care how the constant
441 ; as the original ORR are okay.
453 ; to the original ORR are not okay. In this case we would be replacing the
/external/v8/src/arm64/
Dconstants-arm64.h581 ORR = 0x20000000, enumerator
582 ORN = ORR | NOT,
596 ORR_w_imm = LogicalImmediateFixed | ORR,
597 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
615 ORR_w = LogicalShiftedFixed | ORR,
616 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,

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