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Searched refs:OUT_PKT4 (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_emit.c285 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2); in emit_border_color()
458 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4); in fd5_emit_vertex_bufs()
463 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2); in fd5_emit_vertex_bufs()
472 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1); in fd5_emit_vertex_bufs()
480 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1); in fd5_emit_vertex_bufs()
503 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1); in fd5_emit_state()
521 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1); in fd5_emit_state()
524 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1); in fd5_emit_state()
541 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1); in fd5_emit_state()
550 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2); in fd5_emit_state()
[all …]
Dfd5_gmem.c100 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5); in emit_mrt()
116 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1); in emit_mrt()
125 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4); in emit_mrt()
153 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5); in emit_zs()
164 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1); in emit_zs()
167 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3); in emit_zs()
173 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3); in emit_zs()
177 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2); in emit_zs()
180 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3); in emit_zs()
185 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2); in emit_zs()
[all …]
Dfd5_compute.c69 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1); in cs_program_emit()
72 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 1); in cs_program_emit()
77 OUT_PKT4(ring, REG_A5XX_SP_CS_CTRL_REG0, 1); in cs_program_emit()
84 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1); in cs_program_emit()
89 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1); in cs_program_emit()
93 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1); in cs_program_emit()
99 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2); in cs_program_emit()
103 OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2); in cs_program_emit()
106 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1); in cs_program_emit()
113 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL_0, 2); in cs_program_emit()
[all …]
Dfd5_draw.c55 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2); in draw_impl()
59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1); in draw_impl()
205 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1); in fd5_clear_lrz()
208 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1); in fd5_clear_lrz()
211 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1); in fd5_clear_lrz()
214 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1); in fd5_clear_lrz()
217 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1); in fd5_clear_lrz()
220 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1); in fd5_clear_lrz()
223 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5); in fd5_clear_lrz()
231 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1); in fd5_clear_lrz()
[all …]
Dfd5_program.c372 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5); in fd5_program_emit()
389 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1); in fd5_program_emit()
392 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5); in fd5_program_emit()
404 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5); in fd5_program_emit()
421 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1); in fd5_program_emit()
424 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2); in fd5_program_emit()
428 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2); in fd5_program_emit()
432 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2); in fd5_program_emit()
436 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2); in fd5_program_emit()
440 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2); in fd5_program_emit()
[all …]
Dfd5_blitter.c161 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1); in emit_setup()
164 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1); in emit_setup()
169 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1); in emit_setup()
172 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1); in emit_setup()
175 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2100, 1); in emit_setup()
178 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2180, 1); in emit_setup()
181 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2184, 1); in emit_setup()
184 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1); in emit_setup()
187 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1); in emit_setup()
190 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1); in emit_setup()
[all …]
Dfd5_emit.h104 OUT_PKT4(ring, REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO, 5); in fd5_cache_flush()
158 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1); in fd5_emit_render_cntl()
165 OUT_PKT4(ring, REG_A5XX_GRAS_SC_CNTL, 1); in fd5_emit_render_cntl()
177 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1); in fd5_emit_lrz_flush()
183 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1); in fd5_emit_lrz_flush()
Dfd5_query.c59 OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_CONTROL, 1); in occlusion_resume()
62 OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO, 2); in occlusion_resume()
84 OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_CONTROL, 1); in occlusion_pause()
87 OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO, 2); in occlusion_pause()
/external/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_util.h311 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt) in OUT_PKT4() function
418 OUT_PKT4(ring, reg, 1); in emit_marker5()