Searched refs:OddReg (Results 1 – 4 of 4) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1075 unsigned OddReg = MI->getOperand(1).getReg(); in FixInvalidRegPairOp() local
1077 unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); in FixInvalidRegPairOp()
1111 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
1119 .addReg(OddReg, in FixInvalidRegPairOp()
1135 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1137 OddReg, OddDeadKill, false, in FixInvalidRegPairOp()
1146 if (OddReg == EvenReg && EvenDeadKill) { in FixInvalidRegPairOp()
1159 OddReg, OddDeadKill, OddUndef, in FixInvalidRegPairOp()
1425 unsigned &OddReg, unsigned &BaseReg,
1505 unsigned &OddReg, unsigned &BaseReg, in CanFormLdStDWord() argument
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | FPMover.cpp | 61 unsigned &OddReg) { in getDoubleRegPair() argument
77 OddReg = OddHalvesOfPairs[i]; in getDoubleRegPair()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1624 unsigned OddReg = MI->getOperand(1).getReg(); in FixInvalidRegPairOp() local
1626 unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); in FixInvalidRegPairOp()
1666 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
1674 .addReg(OddReg, in FixInvalidRegPairOp()
1691 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1692 InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill, in FixInvalidRegPairOp()
1697 if (OddReg == EvenReg && EvenDeadKill) { in FixInvalidRegPairOp()
1709 InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill, in FixInvalidRegPairOp()
2019 unsigned &OddReg, unsigned &BaseReg,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1582 unsigned OddReg = MI->getOperand(1).getReg(); in FixInvalidRegPairOp() local
1584 unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); in FixInvalidRegPairOp()
1624 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
1632 .addReg(OddReg, in FixInvalidRegPairOp()
1652 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1654 OddReg, OddDeadKill, false, in FixInvalidRegPairOp()
1662 if (OddReg == EvenReg && EvenDeadKill) { in FixInvalidRegPairOp()
1677 OddReg, OddDeadKill, OddUndef, in FixInvalidRegPairOp()
1974 unsigned &OddReg, unsigned &BaseReg,
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