| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 66 unsigned Offset1,
131 unsigned Offset1, in offsetsCanBeCombined() argument
135 if (Offset0 == Offset1) in offsetsCanBeCombined()
139 if ((Offset0 % Size != 0) || (Offset1 % Size != 0)) in offsetsCanBeCombined()
143 unsigned EltOffset1 = Offset1 / Size; in offsetsCanBeCombined()
182 unsigned Offset1 = MBBI->getOperand(OffsetIdx).getImm() & 0xffff; in findMatchingDSInst() local
185 if (offsetsCanBeCombined(Offset0, Offset1, EltSize)) in findMatchingDSInst()
207 unsigned Offset1 in mergeRead2Pair() local
211 unsigned NewOffset1 = Offset1 / EltSize; in mergeRead2Pair()
303 unsigned Offset1 in mergeWrite2Pair() local
[all …]
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| D | AMDGPUInstrInfo.cpp | 51 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
53 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
59 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
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| D | AMDGPUInstrInfo.h | 50 int64_t Offset1, int64_t Offset2,
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| D | AMDGPUISelDAGToDAG.cpp | 91 SDValue &Offset1) const;
720 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned()
733 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
759 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
776 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
784 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
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| D | SIInstrInfo.cpp | 95 int64_t &Offset1) const { in areLoadsFromSameBasePtr()
128 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue(); in areLoadsFromSameBasePtr()
152 Offset1 = Load1Offset->getZExtValue(); in areLoadsFromSameBasePtr()
186 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); in areLoadsFromSameBasePtr()
232 uint8_t Offset1 = Offset1Imm->getImm(); in getMemOpBaseRegImmOfs() local
234 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) { in getMemOpBaseRegImmOfs()
1344 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
1347 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
1356 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) { in checkInstOffsetsDoNotOverlap()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 93 unsigned Offset1; member
250 if (CI.Offset0 == CI.Offset1) in offsetsCanBeCombined()
254 if ((CI.Offset0 % CI.EltSize != 0) || (CI.Offset1 % CI.EltSize != 0)) in offsetsCanBeCombined()
258 unsigned EltOffset1 = CI.Offset1 / CI.EltSize; in offsetsCanBeCombined()
276 CI.Offset1 = EltOffset1 / 64; in offsetsCanBeCombined()
284 CI.Offset1 = EltOffset1; in offsetsCanBeCombined()
290 CI.BaseOff = std::min(CI.Offset0, CI.Offset1); in offsetsCanBeCombined()
294 CI.Offset1 = (EltOffset1 - CI.BaseOff / CI.EltSize) / 64; in offsetsCanBeCombined()
301 CI.Offset1 = EltOffset1 - CI.BaseOff / CI.EltSize; in offsetsCanBeCombined()
429 CI.Offset1 = MBBI->getOperand(OffsetIdx).getImm(); in findMatchingInst()
[all …]
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| D | SIInstrInfo.cpp | 152 int64_t &Offset1) const { in areLoadsFromSameBasePtr()
185 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue(); in areLoadsFromSameBasePtr()
214 Offset1 = Load1Offset->getZExtValue(); in areLoadsFromSameBasePtr()
248 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); in areLoadsFromSameBasePtr()
294 uint8_t Offset1 = Offset1Imm->getImm(); in getMemOpBaseRegImmOfs() local
296 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) { in getMemOpBaseRegImmOfs()
467 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
469 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
475 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
2121 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
[all …]
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| D | AMDGPUISelDAGToDAG.cpp | 118 SDValue &Offset1) const;
906 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned()
919 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
948 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
965 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
976 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
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| /external/llvm/lib/Fuzzer/test/ |
| D | CustomCrossOverTest.cpp | 43 size_t Offset1 = 0; in LLVMFuzzerCustomCrossOver() local
44 size_t Len1 = R() % (Size1 - Offset1); in LLVMFuzzerCustomCrossOver()
52 memcpy(Out, Data1 + Offset1, Len1); in LLVMFuzzerCustomCrossOver()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 191 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
192 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
193 Offset1 == Offset2) in ClusterNeighboringLoads()
197 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
198 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
201 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 225 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
226 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
227 Offset1 == Offset2) in ClusterNeighboringLoads()
231 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
232 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
235 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 226 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
227 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
228 Offset1 == Offset2) in ClusterNeighboringLoads()
232 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
233 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
236 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.h | 309 int64_t &Offset1, int64_t &Offset2) const;
320 int64_t Offset1, int64_t Offset2,
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 152 int64_t &Offset1, int64_t &Offset2)const;
163 int64_t Offset1, int64_t Offset2,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 292 int Offset1; in apply() local
294 unsigned Base1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply()
299 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetInstrInfo.h | 492 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr() argument
505 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 406 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
418 int64_t Offset1, int64_t Offset2,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 394 int64_t Offset1, Offset2; in ConsecutiveInstr() local
395 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
403 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 213 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
225 int64_t Offset1, int64_t Offset2,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 244 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
256 int64_t Offset1, int64_t Offset2,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 430 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
441 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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| /external/llvm/test/CodeGen/SPARC/ |
| D | 64abi.ll | 505 ; HARD-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
507 ; HARD-DAG: ldx [%sp+[[Offset1]]], %o3
523 ; HARD: st %f0, [%fp+[[Offset1:[0-9]+]]]
528 ; HARD: ld [%fp+[[Offset1]]], %f1
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SPARC/ |
| D | 64abi.ll | 503 ; HARD-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
505 ; HARD-DAG: ldx [%sp+[[Offset1]]], %o3
521 ; HARD: st %f0, [%fp+[[Offset1:[0-9]+]]]
526 ; HARD: ld [%fp+[[Offset1]]], %f1
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1001 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr() argument
1014 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1102 int64_t &Offset1, in areLoadsFromSameBasePtr() argument
1116 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
|