| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 331 const MCConstantExpr *OffsetImm; // Offset immediate value member
681 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && in isMemNoOffset()
692 if (!Memory.OffsetImm) return true; in isAddrMode2()
693 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode2()
712 if (!Memory.OffsetImm) return true; in isAddrMode3()
713 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode3()
733 if (!Memory.OffsetImm) return true; in isAddrMode5()
734 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode5()
781 if (!Memory.OffsetImm) return true; in isMemThumbRIs4()
782 int64_t Val = Memory.OffsetImm->getValue(); in isMemThumbRIs4()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 747 const MCConstantExpr *OffsetImm; // Offset immediate value member
983 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; in isThumbMemPC()
985 Val = Memory.OffsetImm->getValue(); in isThumbMemPC()
1246 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffset()
1256 if (!Memory.OffsetImm) return true; in isMemPCRelImm12()
1257 int64_t Val = Memory.OffsetImm->getValue(); in isMemPCRelImm12()
1341 if (!Memory.OffsetImm) return true; in isAddrMode2()
1342 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode2()
1368 if (!Memory.OffsetImm) return true; in isAddrMode3()
1369 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode3()
[all …]
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 513 const MCConstantExpr *OffsetImm; // Offset immediate value member
740 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; in isThumbMemPC()
742 Val = Memory.OffsetImm->getValue(); in isThumbMemPC()
1094 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && in isMemNoOffset()
1104 if (!Memory.OffsetImm) return true; in isMemPCRelImm12()
1105 int64_t Val = Memory.OffsetImm->getValue(); in isMemPCRelImm12()
1175 if (!Memory.OffsetImm) return true; in isAddrMode2()
1176 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode2()
1199 if (!Memory.OffsetImm) return true; in isAddrMode3()
1200 int64_t Val = Memory.OffsetImm->getValue(); in isAddrMode3()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 433 unsigned OffsetImm = 0; in ReduceLoadStore() local
435 OffsetImm = MI->getOperand(2).getImm(); in ReduceLoadStore()
438 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset) in ReduceLoadStore()
451 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 667 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergeNarrowInsns() local
670 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge"); in mergeNarrowInsns()
671 OffsetImm /= 2; in mergeNarrowInsns()
688 .addImm(OffsetImm) in mergeNarrowInsns()
777 .addImm(OffsetImm) in mergeNarrowInsns()
856 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergePairedInsns() local
859 assert(!(OffsetImm % getMemScale(*RtMI)) && in mergePairedInsns()
861 OffsetImm /= getMemScale(*RtMI); in mergePairedInsns()
872 .addImm(OffsetImm) in mergePairedInsns()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 690 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergeNarrowZeroStores() local
693 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge"); in mergeNarrowZeroStores()
694 OffsetImm /= 2; in mergeNarrowZeroStores()
704 .addImm(OffsetImm) in mergeNarrowZeroStores()
784 int OffsetImm = getLdStOffsetOp(*RtMI).getImm(); in mergePairedInsns() local
787 assert(!(OffsetImm % getMemScale(*RtMI)) && in mergePairedInsns()
789 OffsetImm /= getMemScale(*RtMI); in mergePairedInsns()
821 .addImm(OffsetImm) in mergePairedInsns()
|
| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 541 unsigned OffsetImm = 0; in ReduceLoadStore() local
543 OffsetImm = MI->getOperand(2).getImm(); in ReduceLoadStore()
546 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset) in ReduceLoadStore()
565 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 570 unsigned OffsetImm = 0; in ReduceLoadStore() local
572 OffsetImm = MI->getOperand(2).getImm(); in ReduceLoadStore()
575 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset) in ReduceLoadStore()
594 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.cpp | 5766 int32_t OffsetImm = 0; in formAddressingMode() local
5804 dumpAddressOpt(Func, BaseVar, OffsetImm, OffsetReg, OffsetRegShamt, in formAddressingMode()
5809 if (matchAssign(VMetadata, &BaseVar, &OffsetImm, &Reason)) { in formAddressingMode()
5814 matchAssign(VMetadata, &OffsetReg, &OffsetImm, &Reason)) { in formAddressingMode()
5837 if (matchOffsetBase(VMetadata, &BaseVar, &OffsetImm, &Reason)) { in formAddressingMode()
5853 Context.insert<InstAssign>(BaseVar, Ctx->getConstantInt32(OffsetImm)); in formAddressingMode()
5854 OffsetImm = 0; in formAddressingMode()
5855 } else if (OffsetImm != 0) { in formAddressingMode()
5859 const int32_t PositiveOffset = OffsetImm > 0 ? OffsetImm : -OffsetImm; in formAddressingMode()
5861 OffsetImm > 0 ? InstArithmetic::Add : InstArithmetic::Sub; in formAddressingMode()
[all …]
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| D | IceTargetLoweringMIPS32.cpp | 5366 int32_t OffsetImm = 0; in formAddressingMode() local
5389 dumpAddressOpt(Func, BaseVar, OffsetImm, Reason); in formAddressingMode()
5393 if (matchAssign(VMetadata, &BaseVar, &OffsetImm, &Reason)) { in formAddressingMode()
5397 if (matchOffsetBase(VMetadata, &BaseVar, &OffsetImm, &Reason)) { in formAddressingMode()
5407 Context.insert<InstAssign>(BaseVar, Ctx->getConstantInt32(OffsetImm)); in formAddressingMode()
5408 OffsetImm = 0; in formAddressingMode()
5409 } else if (OffsetImm != 0) { in formAddressingMode()
5412 const int32_t PositiveOffset = OffsetImm > 0 ? OffsetImm : -OffsetImm; in formAddressingMode()
5414 OffsetImm > 0 ? InstArithmetic::Add : InstArithmetic::Sub; in formAddressingMode()
5416 if (!OperandMIPS32Mem::canHoldOffset(Ty, ZeroExt, OffsetImm)) { in formAddressingMode()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 211 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
213 if (OffsetImm) { in getMemOpBaseRegImmOfs()
219 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
269 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
272 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
277 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
279 if (!OffsetImm) in getMemOpBaseRegImmOfs()
285 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 273 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
275 if (OffsetImm) { in getMemOpBaseRegImmOfs()
281 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
332 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
335 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
344 const MachineOperand *OffsetImm = in getMemOpBaseRegImmOfs() local
346 if (!OffsetImm) in getMemOpBaseRegImmOfs()
352 Offset = OffsetImm->getImm(); in getMemOpBaseRegImmOfs()
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