| /external/capstone/arch/XCore/ |
| D | XCoreDisassembler.c | 216 unsigned *Op1, unsigned *Op2, unsigned *Op3) in Decode3OpInstruction() argument
228 *Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2); in Decode3OpInstruction()
509 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
510 DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); in Decode3RInstruction()
514 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
523 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
524 DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); in Decode3RImmInstruction()
528 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
537 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
538 DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); in Decode2RUSInstruction()
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 260 unsigned &Op3) { in Decode3OpInstruction() argument
270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
539 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
552 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
565 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 260 unsigned &Op3) { in Decode3OpInstruction() argument
270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
539 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
552 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
565 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
[all …]
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| /external/tensorflow/tensorflow/core/api_def/ |
| D | update_api_def_test.cc | 87 REGISTER_OP("Op3") in TEST()
107 REGISTER_OP("Op3") in TEST()
111 Summary for Op3. in TEST()
130 name: "Op3" in TEST()
134 summary: "Summary for Op3." in TEST()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAGInfo.h | 60 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemcpy() argument
77 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
93 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemset() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 54 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
70 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
95 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
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| D | SelectionDAG.h | 1152 SDValue Op3);
1154 SDValue Op3, SDValue Op4);
1156 SDValue Op3, SDValue Op4, SDValue Op5);
1171 SDValue Op1, SDValue Op2, SDValue Op3);
1208 SDValue Op1, SDValue Op2, SDValue Op3);
1214 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1221 SDValue Op3);
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
80 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
92 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
|
| D | SelectionDAG.h | 1004 SDValue Op3);
1006 SDValue Op3, SDValue Op4);
1008 SDValue Op3, SDValue Op4, SDValue Op5);
1020 SDValue Op1, SDValue Op2, SDValue Op3);
1035 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1037 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
1058 SDValue Op1, SDValue Op2, SDValue Op3);
1068 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1075 SDValue Op3);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 111 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
112 if (Op3.isGlobal()) in getAddressFromInstr()
113 AM.GV = Op3.getGlobal(); in getAddressFromInstr()
115 AM.Disp = Op3.getImm(); in getAddressFromInstr()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86CodeEmitter.cpp | 441 const MachineOperand &Op3 = MI.getOperand(Op+3); in emitMemModRMByte() local
446 if (Op3.isGlobal()) { in emitMemModRMByte()
447 DispForReloc = &Op3; in emitMemModRMByte()
448 } else if (Op3.isSymbol()) { in emitMemModRMByte()
449 DispForReloc = &Op3; in emitMemModRMByte()
450 } else if (Op3.isCPI()) { in emitMemModRMByte()
452 DispForReloc = &Op3; in emitMemModRMByte()
454 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); in emitMemModRMByte()
455 DispVal += Op3.getOffset(); in emitMemModRMByte()
457 } else if (Op3.isJTI()) { in emitMemModRMByte()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 710 SDValue Op3);
712 SDValue Op3, SDValue Op4);
714 SDValue Op3, SDValue Op4, SDValue Op5);
727 SDValue Op1, SDValue Op2, SDValue Op3);
743 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
745 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
766 SDValue Op1, SDValue Op2, SDValue Op3);
775 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
781 EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreSelectionDAGInfo.h | 27 SDValue Op3, unsigned Align, bool isVolatile,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreSelectionDAGInfo.h | 27 SDValue Op3, unsigned Align, bool isVolatile,
|
| /external/grpc-grpc/include/grpcpp/impl/codegen/ |
| D | call.h | 616 class Op3 = CallNoOp<3>, class Op4 = CallNoOp<4>,
621 public Op3,
630 this->Op3::AddOp(ops, nops); in FillOps()
641 this->Op3::FinishOp(status); in FinalizeResult()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/AsmParser/ |
| D | BPFAsmParser.cpp | 269 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; in PreMatchCheck() local
270 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
276 && Op0.getReg() != Op3.getReg()) in PreMatchCheck()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXSelectionDAGInfo.h | 45 SDValue Op3, unsigned Align,
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 70 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
74 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
77 switch (Op3.getImm()) { in printInst()
110 if (Op2.isImm() && Op3.isImm()) { in printInst()
114 int64_t imms = Op3.getImm(); in printInst()
144 if (Op2.getImm() > Op3.getImm()) { in printInst()
147 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
155 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 61 SDValue Op3, unsigned Align,
|
| /external/capstone/arch/AArch64/ |
| D | AArch64InstPrinter.c | 83 MCOperand *Op3 = MCInst_getOperand(MI, 3); in AArch64_printInst() local
88 if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) { in AArch64_printInst()
91 switch (MCOperand_getImm(Op3)) { in AArch64_printInst()
136 if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) { in AArch64_printInst()
140 int64_t imms = MCOperand_getImm(Op3); in AArch64_printInst()
189 if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) { in AArch64_printInst()
195 printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1); in AArch64_printInst()
210 …nsn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1; in AArch64_printInst()
223 printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1); in AArch64_printInst()
238 …m64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm… in AArch64_printInst()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 58 SDValue Op3, unsigned Align, bool isVolatile,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 58 SDValue Op3, unsigned Align, bool isVolatile,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4350 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4351 if (Op2.isScalarReg() && Op3.isImm()) { in MatchAndEmitInstruction()
4352 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
4372 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
4373 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in MatchAndEmitInstruction()
4374 Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
4436 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
4439 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4440 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
4455 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 79 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
83 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
86 switch (Op3.getImm()) { in printInst()
119 if (Op2.isImm() && Op3.isImm()) { in printInst()
123 int64_t imms = Op3.getImm(); in printInst()
153 if (Op2.getImm() > Op3.getImm()) { in printInst()
156 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
164 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3752 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
3753 if (Op2.isReg() && Op3.isImm()) { in MatchAndEmitInstruction()
3754 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
3774 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
3775 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in MatchAndEmitInstruction()
3776 Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
3838 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
3841 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3842 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
3857 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
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