| /external/capstone/arch/XCore/ |
| D | XCoreDisassembler.c | 626 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
632 S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6); in DecodeL6RInstruction()
637 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
667 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
673 S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5); in DecodeL5RInstruction()
678 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
689 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
694 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
698 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
709 unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
657 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
682 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
692 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
708 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
711 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
722 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
657 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
682 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
692 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
708 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
711 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
722 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /external/grpc-grpc/include/grpcpp/impl/codegen/ |
| D | call.h | 616 class Op3 = CallNoOp<3>, class Op4 = CallNoOp<4>,
622 public Op4,
631 this->Op4::AddOp(ops, nops); in FillOps()
642 this->Op4::FinishOp(status); in FinalizeResult()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3839 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
3841 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3843 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
3860 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
3872 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
3882 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
3903 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
3905 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3907 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
3924 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4437 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
4439 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4441 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
4458 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
4470 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
4480 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
4501 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
4503 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4505 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
4522 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 712 SDValue Op3, SDValue Op4);
714 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1305 SDValue Op4 = Node->getOperand(4); in Select() local
1306 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2234 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
2240 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
2249 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
|
| D | X86ISelLowering.cpp | 10190 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); in LowerMEMBARRIER() local
10193 if (!Op1 && !Op2 && !Op3 && Op4) in LowerMEMBARRIER()
10197 if (Op1 && !Op2 && !Op3 && !Op4) in LowerMEMBARRIER()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1006 SDValue Op3, SDValue Op4);
1008 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1154 SDValue Op3, SDValue Op4);
1156 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1511 SDValue Op4 = Node->getOperand(4); in Select() local
1513 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2698 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
2710 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
2719 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 3393 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
3405 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
3414 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 4737 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
4738 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
4744 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
4745 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5753 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm() local
5754 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
5758 auto Op4Reg = Op4.getReg(); in tryConvertingToTwoOperandForm()
5802 LastOp = &Op4; in tryConvertingToTwoOperandForm()
5823 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5544 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm() local
5545 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
5549 auto Op4Reg = Op4.getReg(); in tryConvertingToTwoOperandForm()
5593 LastOp = &Op4; in tryConvertingToTwoOperandForm()
5614 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5782 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
5783 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
5789 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
5790 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 6959 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
6960 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
6966 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
6967 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|