| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 74 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
141 expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) { in expandArith() argument
158 auto MIBHI = buildMI(MBB, MBBI, OpHi) in expandArith()
327 unsigned OpLo, OpHi, DstLoReg, DstHiReg; in expand() local
336 OpHi = AVR::SBCIRdK; in expand()
347 auto MIBHI = buildMI(MBB, MBBI, OpHi) in expand()
390 unsigned OpLo, OpHi, DstLoReg, DstHiReg; in expand() local
396 OpHi = AVR::COMRd; in expand()
406 auto MIBHI = buildMI(MBB, MBBI, OpHi) in expand()
420 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1075 SDValue OpHi = Op; in SplitVecRes_StrictFPOp() local
1082 GetSplitVector(Op, OpLo, OpHi); in SplitVecRes_StrictFPOp()
1084 std::tie(OpLo, OpHi) = DAG.SplitVectorOperand(N, i); in SplitVecRes_StrictFPOp()
1088 OpsHi.push_back(OpHi); in SplitVecRes_StrictFPOp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstPropagation.cpp | 1952 const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1); in evaluate() local
1954 Register SrcRL(OpLo), SrcRH(OpHi); in evaluate()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 14012 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); in LowerAVXExtend() local
14018 OpHi = DAG.getBitcast(HVT, OpHi); in LowerAVXExtend()
14020 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); in LowerAVXExtend()
14161 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, in LowerTRUNCATE() local
14164 OpHi = DAG.getBitcast(MVT::v4i32, OpHi); in LowerTRUNCATE()
14166 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask); in LowerTRUNCATE()
14202 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In, in LowerTRUNCATE() local
14206 OpHi = DAG.getBitcast(MVT::v16i8, OpHi); in LowerTRUNCATE()
14214 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1); in LowerTRUNCATE()
14217 OpHi = DAG.getBitcast(MVT::v4i32, OpHi); in LowerTRUNCATE()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 16933 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); in LowerAVXExtend() local
16939 OpHi = DAG.getBitcast(HVT, OpHi); in LowerAVXExtend()
16941 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); in LowerAVXExtend()
17270 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, in LowerTRUNCATE() local
17273 OpHi = DAG.getBitcast(MVT::v4i32, OpHi); in LowerTRUNCATE()
17275 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask); in LowerTRUNCATE()
17301 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In, in LowerTRUNCATE() local
17305 OpHi = DAG.getBitcast(MVT::v16i8, OpHi); in LowerTRUNCATE()
17312 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, OpHi, ShufMask1); in LowerTRUNCATE()
17315 OpHi = DAG.getBitcast(MVT::v4i32, OpHi); in LowerTRUNCATE()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 3560 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi, in splitUnaryVectorOp() local
3563 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
3583 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, in splitBinaryVectorOp() local
3586 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
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