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Searched refs:OpRC (Results 1 – 9 of 9) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DBreakFalseDeps.cpp126 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
133 !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
145 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
DMachineInstr.cpp721 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
727 if (OpRC) in getRegClassConstraintEffect()
728 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
731 } else if (OpRC) in getRegClassConstraintEffect()
732 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineRegisterInfo.cpp82 const TargetRegisterClass *OpRC = in recomputeRegClass() local
84 if (OpRC) in recomputeRegClass()
85 NewRC = TRI->getCommonSubClass(NewRC, OpRC); in recomputeRegClass()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp333 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
335 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
337 if (OpRC) { in AddRegisterOperand()
339 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); in AddRegisterOperand()
341 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
342 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
343 unsigned NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
399 const TargetRegisterClass *OpRC = in AddOperand() local
405 if (OpRC && IIRC && OpRC != IIRC && in AddOperand()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp1764 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
1765 unsigned TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1769 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
1770 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
1772 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1786 unsigned VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1806 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1807 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1808 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1810 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp2236 const TargetRegisterClass *OpRC = in legalizeOperands() local
2238 if (RI.hasVGPRs(OpRC)) { in legalizeOperands()
2239 VRC = OpRC; in legalizeOperands()
2241 SRC = OpRC; in legalizeOperands()
2290 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
2291 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
2292 if (VRC == OpRC) in legalizeOperands()
3003 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
3004 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); in findUsedSGPR()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp1246 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
1252 if (OpRC) in getRegClassConstraintEffect()
1253 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
1256 } else if (OpRC) in getRegClassConstraintEffect()
1257 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp3455 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
3459 if (DstRC == OpRC) in legalizeGenericOperand()
3509 const TargetRegisterClass *OpRC = in legalizeOperands() local
3511 if (RI.hasVGPRs(OpRC)) { in legalizeOperands()
3512 VRC = OpRC; in legalizeOperands()
3514 SRC = OpRC; in legalizeOperands()
3562 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
3563 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
3564 if (VRC == OpRC) in legalizeOperands()
4615 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1879 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1881 return OpRC->hasSubClassEq(RRC); in validateReg()