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Searched refs:OpSize32 (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrSystem.td82 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
92 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
102 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
112 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
173 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
180 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
187 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
194 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
215 OpSize32;
218 OpSize32;
[all …]
DX86InstrExtension.td20 "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
27 "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
54 OpSize32, Sched<[WriteALU]>;
58 OpSize32, Sched<[WriteALULd]>;
62 OpSize32, Sched<[WriteALU]>;
66 OpSize32, TB, Sched<[WriteALULd]>;
80 OpSize32, Sched<[WriteALU]>;
84 OpSize32, Sched<[WriteALULd]>;
88 OpSize32, Sched<[WriteALU]>;
92 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrControl.td25 "ret{l}", [], IIC_RET>, OpSize32,
28 "ret{q}", [], IIC_RET>, OpSize32,
35 [], IIC_RET_IMM>, OpSize32,
39 [], IIC_RET_IMM>, OpSize32,
45 "{l}ret{l|f}", [], IIC_RET>, OpSize32;
51 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
63 IIC_IRET>, OpSize32;
79 "jmp\t$dst", [], IIC_JMP_REL>, OpSize32;
92 [], IIC_Jcc>, TB, OpSize32;
144 OpSize32, Sched<[WriteJump]>;
[all …]
DX86InstrShiftRotate.td28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
46 OpSize32;
62 "shl{l}\t$dst", [], IIC_SR>, OpSize32;
83 OpSize32;
99 IIC_SR>, OpSize32;
117 IIC_SR>, OpSize32;
134 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
150 IIC_SR>, OpSize32;
164 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
183 OpSize32;
[all …]
DX86InstrInfo.td1064 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
1097 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1103 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1105 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1112 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1116 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1124 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1127 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1135 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1171 OpSize32, Requires<[Not64BitMode]>;
[all …]
DX86InstrArithmetic.td27 OpSize32, Requires<[Not64BitMode]>;
33 OpSize32, Requires<[In64BitMode]>;
77 IIC_MUL32_REG>, OpSize32, Sched<[WriteIMul]>;
103 [], IIC_MUL32_MEM>, OpSize32, SchedLoadReg<WriteIMulLd>;
122 IIC_IMUL32_RR>, OpSize32, Sched<[WriteIMul]>;
141 "imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize32,
166 TB, OpSize32;
190 TB, OpSize32;
224 IIC_IMUL32_RRI>, OpSize32;
230 IIC_IMUL32_RRI>, OpSize32;
[all …]
DX86InstrCMovSetCC.td31 IIC_CMOV32_RR>, TB, OpSize32;
53 TB, OpSize32;
DX86InstrTSX.td30 "xbegin\t$dst", []>, OpSize32, Requires<[HasRTM]>;
DX86InstrCompiler.td390 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
402 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
421 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
436 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
581 IIC_ALU_MEM>, Requires<[Not64BitMode]>, OpSize32, LOCK,
620 IIC_ALU_NONMEM>, OpSize32, LOCK;
652 IIC_ALU_MEM>, OpSize32, LOCK;
676 IIC_ALU_MEM>, OpSize32, LOCK;
711 IIC_UNARY_MEM>, OpSize32, LOCK;
748 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
[all …]
DX86InstrFormats.td151 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
165 class OpSize32 { OperandSize OpSize = OpSize32; }
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrControl.td25 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
27 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
31 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
33 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
37 "{l}ret{l|f}", []>, OpSize32;
43 "{l}ret{l|f}\t$amt", []>, OpSize32;
54 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
69 "jmp\t$dst", []>, OpSize32;
82 []>, TB, OpSize32;
132 OpSize32, Sched<[WriteJump]>;
[all …]
DX86InstrExtension.td20 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
27 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
52 OpSize32, Sched<[WriteALU]>;
56 OpSize32, Sched<[WriteALULd]>;
60 OpSize32, Sched<[WriteALU]>;
64 OpSize32, TB, Sched<[WriteALULd]>;
78 OpSize32, Sched<[WriteALU]>;
82 OpSize32, Sched<[WriteALULd]>;
86 OpSize32, Sched<[WriteALU]>;
90 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrSystem.td78 OpSize32;
88 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
97 OpSize32;
107 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
169 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
179 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
206 OpSize32, NotMemoryFoldable;
209 OpSize32, NotMemoryFoldable;
229 OpSize32, NotMemoryFoldable;
232 OpSize32, NotMemoryFoldable;
[all …]
DX86InstrShiftRotate.td28 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
46 OpSize32;
61 "shl{l}\t$dst", []>, OpSize32;
82 OpSize32;
98 OpSize32;
115 OpSize32;
132 [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32;
148 OpSize32;
162 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>, OpSize32;
181 OpSize32;
[all …]
DX86InstrInfo.td1161 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1169 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1204 OpSize32, Requires<[Not64BitMode]>;
1210 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1217 OpSize32, Requires<[Not64BitMode]>;
1224 OpSize32, Requires<[Not64BitMode]>;
1230 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1239 "push{l}\t$imm", []>, OpSize32,
1242 "push{l}\t$imm", []>, OpSize32,
1250 OpSize32, Requires<[Not64BitMode]>;
[all …]
DX86InstrArithmetic.td27 OpSize32, Requires<[Not64BitMode]>;
33 OpSize32, Requires<[In64BitMode]>;
77 OpSize32, Sched<[WriteIMul]>;
101 "mul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul.Folded>;
121 OpSize32, Sched<[WriteIMul]>;
139 "imul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul.Folded>;
164 Sched<[WriteIMul]>, TB, OpSize32;
185 Sched<[WriteIMul.Folded, ReadAfterLd]>, TB, OpSize32;
216 Sched<[WriteIMul]>, OpSize32;
222 Sched<[WriteIMul]>, OpSize32;
[all …]
DX86InstrCMovSetCC.td32 TB, OpSize32;
51 CondNode, EFLAGS))]>, TB, OpSize32;
DX86InstrTSX.td32 "xbegin\t$dst", []>, OpSize32;
DX86InstrCompiler.td406 [(X86rep_movs i32)]>, REP, OpSize32,
418 [(X86rep_movs i32)]>, REP, OpSize32,
437 [(X86rep_stos i32)]>, REP, OpSize32,
452 [(X86rep_stos i32)]>, REP, OpSize32,
598 Requires<[Not64BitMode]>, OpSize32, LOCK,
636 OpSize32, LOCK;
666 OpSize32, LOCK;
690 OpSize32, LOCK;
724 OpSize32, LOCK;
781 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK;
[all …]
DX86InstrFormats.td168 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
182 class OpSize32 { OperandSize OpSize = OpSize32; }
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.h137 OpSize16 = 1, OpSize32 = 2 enumerator
DX86RecognizableInstr.cpp807 } else if(OpSize == X86Local::OpSize32) { in typeFromString()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h334 OpSize32 = 2 << OpSizeShift, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h378 OpSize32 = 2 << OpSizeShift, enumerator
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp131 OpSize16 = 1, OpSize32 = 2 enumerator
925 } else if(OpSize == X86Local::OpSize32) { in typeFromString()

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