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Searched refs:OpType (Results 1 – 25 of 55) sorted by relevance

123

/external/skqp/tools/bookmaker/
Ddefinition.cpp39 enum class OpType : int8_t { enum
65 OpType fReturnType;
70 OpType fType;
74 { DEFOP::kUnknown, "??", "???", BLANK, OpType::kNone, OpMod::kNone, BLANK,
76 { DEFOP::kAdd, "+", "add", BLANK, OpType::kThis, OpMod::kNone, BLANK,
77 {{ CONST, OpType::kThis, OpMod::kReference, },
78 { CONST, OpType::kThis, OpMod::kReference, }}},
79 { DEFOP::kAddTo, "+=", "addto", BLANK, OpType::kVoid, OpMod::kNone, BLANK,
80 {{ CONST, OpType::kThis, OpMod::kReference, }}},
81 { DEFOP::kAddTo, "+=", "addto1", BLANK, OpType::kThis, OpMod::kReference, BLANK,
[all …]
/external/skia/tools/bookmaker/
Ddefinition.cpp39 enum class OpType : int8_t { enum
65 OpType fReturnType;
70 OpType fType;
74 { DEFOP::kUnknown, "??", "???", BLANK, OpType::kNone, OpMod::kNone, BLANK,
76 { DEFOP::kAdd, "+", "add", BLANK, OpType::kThis, OpMod::kNone, BLANK,
77 {{ CONST, OpType::kThis, OpMod::kReference, },
78 { CONST, OpType::kThis, OpMod::kReference, }}},
79 { DEFOP::kAddTo, "+=", "addto", BLANK, OpType::kVoid, OpMod::kNone, BLANK,
80 {{ CONST, OpType::kThis, OpMod::kReference, }}},
81 { DEFOP::kAddTo, "+=", "addto1", BLANK, OpType::kThis, OpMod::kReference, BLANK,
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCWin64EH.h29 typedef Win64EH::UnwindOpcodes OpType; typedef
31 OpType Operation;
36 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg) in MCWin64EHInstruction()
43 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg, unsigned Off) in MCWin64EHInstruction()
51 MCWin64EHInstruction(OpType Op, MCSymbol *L, bool Code) in MCWin64EHInstruction()
55 OpType getOperation() const { return Operation; } in getOperation()
DMCDwarf.h232 enum OpType { SameValue, Remember, Restore, Move, RelMove }; enum
234 OpType Operation;
240 MCCFIInstruction(OpType Op, MCSymbol *L) in MCCFIInstruction()
244 MCCFIInstruction(OpType Op, MCSymbol *L, unsigned Register) in MCCFIInstruction()
252 MCCFIInstruction(OpType Op, MCSymbol *L, const MachineLocation &D, in MCCFIInstruction()
257 OpType getOperation() const { return Operation; } in getOperation()
/external/tensorflow/tensorflow/lite/kernels/
Dmaximum_minimum.cc99 template <KernelType kernel_type, typename OpType>
106 TFLiteOperation<float, OpType>(context, node, op_context); in Eval()
109 TFLiteOperation<uint8_t, OpType>(context, node, op_context); in Eval()
112 TFLiteOperation<int8_t, OpType>(context, node, op_context); in Eval()
115 TFLiteOperation<int32_t, OpType>(context, node, op_context); in Eval()
118 TFLiteOperation<int64_t, OpType>(context, node, op_context); in Eval()
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DLowLevel.cpp110 #define TestRegReg(Inst, Dst, Src, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
113 "(" #Inst ", " #Dst ", " #Src ", " #OpType ", " #ByteCountUntyped \ in TEST_F()
116 __ Inst(IceType_##OpType, GPRRegister::Encoded_Reg_##Dst, \ in TEST_F()
124 #define TestRegImm(Inst, Dst, Imm, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
127 "(" #Inst ", " #Dst ", " #Imm ", " #OpType ", " #ByteCountUntyped \ in TEST_F()
130 __ Inst(IceType_##OpType, GPRRegister::Encoded_Reg_##Dst, Immediate(Imm)); \ in TEST_F()
137 #define TestRegAbsoluteAddr(Inst, Dst, Disp, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
140 "(" #Inst ", " #Dst ", " #Disp ", " #OpType ", " #ByteCountUntyped \ in TEST_F()
143 __ Inst(IceType_##OpType, GPRRegister::Encoded_Reg_##Dst, \ in TEST_F()
151 #define TestRegAddrBase(Inst, Dst, Base, Disp, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DAsmWriterInst.h28 enum OpType { enum
53 AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {} in OperandType()
56 OpType op = isLiteralTextOperand)
62 OpType op = isMachineInstrOperand)
/external/llvm/utils/TableGen/
DAsmWriterInst.h28 enum OpType { enum
53 AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {} in OperandType()
56 OpType op = isLiteralTextOperand)
62 OpType op = isMachineInstrOperand)
/external/swiftshader/third_party/LLVM/utils/TableGen/
DAsmWriterInst.h28 enum OpType { enum
57 AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {} in OperandType()
60 OpType op = isLiteralTextOperand)
67 OpType op = isMachineInstrOperand)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h174 bool opCanUseLiteralConstant(unsigned OpType) const { in opCanUseLiteralConstant() argument
176 return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST && in opCanUseLiteralConstant()
177 OpType <= AMDGPU::OPERAND_REG_IMM_LAST; in opCanUseLiteralConstant()
183 bool opCanUseInlineConstant(unsigned OpType) const { in opCanUseInlineConstant() argument
184 return OpType >= AMDGPU::OPERAND_SRC_FIRST && in opCanUseInlineConstant()
185 OpType <= AMDGPU::OPERAND_SRC_LAST; in opCanUseInlineConstant()
/external/tensorflow/tensorflow/lite/toco/graph_transformations/
Dfuse_binary_into_preceding_affine.cc65 enum class OpType { BiasPlusOperand, BiasMinusOperand, OperandMinusBias }; in FuseAddOrSubParamsIntoPrecedingAffine() enum
67 const OpType optype = (add_or_sub_op->type == OperatorType::kAdd) in FuseAddOrSubParamsIntoPrecedingAffine()
68 ? OpType::BiasPlusOperand in FuseAddOrSubParamsIntoPrecedingAffine()
70 ? OpType::BiasMinusOperand in FuseAddOrSubParamsIntoPrecedingAffine()
71 : OpType::OperandMinusBias; in FuseAddOrSubParamsIntoPrecedingAffine()
77 if (optype == OpType::BiasPlusOperand) { in FuseAddOrSubParamsIntoPrecedingAffine()
79 } else if (optype == OpType::BiasMinusOperand) { in FuseAddOrSubParamsIntoPrecedingAffine()
81 } else if (optype == OpType::OperandMinusBias) { in FuseAddOrSubParamsIntoPrecedingAffine()
/external/tensorflow/tensorflow/cc/gradients/
Dimage_grad_test.cc40 enum OpType { RESIZE_NEAREST, RESIZE_BILINEAR, RESIZE_BICUBIC }; enum in tensorflow::__anon0dcd93d60111::ImageGradTest
54 void MakeOp(const OpType op_type, const Tensor& x_data, const Input& y_shape, in MakeOp()
79 void TestResizedShapeForType(const OpType op_type, const bool align_corners, in TestResizedShapeForType()
94 void TestResizedShape(OpType op_type) { in TestResizedShape()
111 void TestResizeToSmallerAndAlign(const OpType op_type, in TestResizeToSmallerAndAlign()
126 void TestResizeToLargerAndAlign(const OpType op_type, in TestResizeToLargerAndAlign()
141 void TestResize(OpType op_type) { in TestResize()
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DLowLevel.cpp157 #define TestRegReg(Inst, Dst, Src, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
160 "(" #Inst ", " #Dst ", " #Src ", " #OpType ", " #ByteCountUntyped \ in TEST_F()
163 __ Inst(IceType_##OpType, Encoded_GPR_##Dst(), Encoded_GPR_##Src()); \ in TEST_F()
170 #define TestRegImm(Inst, Dst, Imm, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
173 "(" #Inst ", " #Dst ", " #Imm ", " #OpType ", " #ByteCountUntyped \ in TEST_F()
176 __ Inst(IceType_##OpType, Encoded_GPR_##Dst(), Immediate(Imm)); \ in TEST_F()
183 #define TestRegAbsoluteAddr(Inst, Dst, Disp, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
186 "(" #Inst ", " #Dst ", " #Disp ", " #OpType ", " #ByteCountUntyped \ in TEST_F()
189 __ Inst(IceType_##OpType, Encoded_GPR_##Dst(), Address::Absolute(Disp)); \ in TEST_F()
196 #define TestRegAddrBase(Inst, Dst, Base, Disp, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
[all …]
/external/llvm/include/llvm/MC/
DMCDwarf.h327 enum OpType { enum
346 OpType Operation;
355 MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, StringRef V) in MCCFIInstruction()
361 MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R1, unsigned R2) in MCCFIInstruction()
461 OpType getOperation() const { return Operation; } in getOperation()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Utils/
DAMDGPUBaseInfo.cpp758 unsigned OpType = Desc.OpInfo[OpNo].OperandType; in isSISrcOperand() local
759 return OpType >= AMDGPU::OPERAND_SRC_FIRST && in isSISrcOperand()
760 OpType <= AMDGPU::OPERAND_SRC_LAST; in isSISrcOperand()
765 unsigned OpType = Desc.OpInfo[OpNo].OperandType; in isSISrcFPOperand() local
766 switch (OpType) { in isSISrcFPOperand()
782 unsigned OpType = Desc.OpInfo[OpNo].OperandType; in isSISrcInlinableOperand() local
783 return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST && in isSISrcInlinableOperand()
784 OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST; in isSISrcInlinableOperand()
/external/skia/tools/mdbviz/
DModel.cpp69 SkDrawCommand::OpType type = fOps[index]->getType(); in isHierarchyPush()
77 SkDrawCommand::OpType type = fOps[index]->getType(); in isHierarchyPop()
/external/skqp/tools/mdbviz/
DModel.cpp69 SkDrawCommand::OpType type = fOps[index]->getType(); in isHierarchyPush()
77 SkDrawCommand::OpType type = fOps[index]->getType(); in isHierarchyPop()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCDwarf.h418 enum OpType { enum
437 OpType Operation;
446 MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, StringRef V) in MCCFIInstruction()
452 MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R1, unsigned R2) in MCCFIInstruction()
552 OpType getOperation() const { return Operation; } in getOperation()
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp80 unsigned OpType = Desc.OpInfo[OpNo].OperandType; in isSrcOperand() local
82 return OpType == AMDGPU::OPERAND_REG_IMM32 || in isSrcOperand()
83 OpType == AMDGPU::OPERAND_REG_INLINE_C; in isSrcOperand()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h148 bool opCanUseLiteralConstant(unsigned OpType) const;
153 bool opCanUseInlineConstant(unsigned OpType) const;
DSIRegisterInfo.cpp894 bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const { in opCanUseLiteralConstant()
895 return OpType == AMDGPU::OPERAND_REG_IMM32; in opCanUseLiteralConstant()
898 bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const { in opCanUseInlineConstant()
899 if (opCanUseLiteralConstant(OpType)) in opCanUseInlineConstant()
902 return OpType == AMDGPU::OPERAND_REG_INLINE_C; in opCanUseInlineConstant()
/external/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/
DNaClBitcodeDecoders.h47 bool DecodeBinaryOpcode(uint64_t NaClOpcode, Type *OpType,
/external/tensorflow/tensorflow/core/util/
Dstat_summarizer.cc90 std::string OpType(const DeviceStepStats& ds, const NodeExecStats& ns) { in OpType() function
173 op_type = OpType(ds, ns); in ProcessStepStats()
/external/skqp/tools/debugger/
DSkDrawCommand.h28 enum OpType { enum
75 SkDrawCommand(OpType opType);
93 static const char* GetCommandString(OpType type);
117 OpType fOpType;
/external/skia/tools/debugger/
DSkDrawCommand.h28 enum OpType { enum
75 SkDrawCommand(OpType opType);
93 static const char* GetCommandString(OpType type);
117 OpType fOpType;

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