| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 97 unsigned OtherReg = in getRegAllocationHints() local
99 if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass) in getRegAllocationHints()
100 Worklist.push_back(OtherReg); in getRegAllocationHints()
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| D | SystemZShortenInst.cpp | 89 unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx); in shortenIIF() local
90 if (LiveRegs.contains(OtherReg)) in shortenIIF()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 89 unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx); in shortenIIF() local
90 if (LiveRegs.contains(OtherReg)) in shortenIIF()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 321 unsigned OtherReg = Hint.second; in updateRegAllocHint() local
322 Hint = MRI->getRegAllocationHint(OtherReg); in updateRegAllocHint()
325 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
329 : ARMRI::RegPairOdd, OtherReg); in updateRegAllocHint()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 349 unsigned OtherReg = Hint.second; in updateRegAllocHint() local
350 Hint = MRI->getRegAllocationHint(OtherReg); in updateRegAllocHint()
353 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
357 : ARMRI::RegPairOdd, OtherReg); in updateRegAllocHint()
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| /external/llvm/lib/CodeGen/ |
| D | RegAllocGreedy.cpp | 2322 unsigned OtherReg = Instr.getOperand(0).getReg(); in collectHintInfo() local
2323 if (OtherReg == Reg) { in collectHintInfo()
2324 OtherReg = Instr.getOperand(1).getReg(); in collectHintInfo()
2325 if (OtherReg == Reg) in collectHintInfo()
2329 unsigned OtherPhysReg = TargetRegisterInfo::isPhysicalRegister(OtherReg) in collectHintInfo()
2330 ? OtherReg in collectHintInfo()
2331 : VRM->getPhys(OtherReg); in collectHintInfo()
2333 Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg, in collectHintInfo()
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| D | RegisterCoalescer.cpp | 2860 unsigned OtherReg, OtherSubReg, OtherSrcReg, OtherSrcSubReg; in applyTerminalRule() local
2861 isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg, in applyTerminalRule()
2863 if (OtherReg == SrcReg) in applyTerminalRule()
2864 OtherReg = OtherSrcReg; in applyTerminalRule()
2866 if (TargetRegisterInfo::isPhysicalRegister(OtherReg) || in applyTerminalRule()
2867 isTerminalReg(OtherReg, MI, MRI)) in applyTerminalRule()
2870 if (LIS->getInterval(OtherReg).overlaps(DstLI)) { in applyTerminalRule()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegAllocGreedy.cpp | 2831 unsigned OtherReg = Instr.getOperand(0).getReg(); in collectHintInfo() local
2832 if (OtherReg == Reg) { in collectHintInfo()
2833 OtherReg = Instr.getOperand(1).getReg(); in collectHintInfo()
2834 if (OtherReg == Reg) in collectHintInfo()
2838 unsigned OtherPhysReg = TargetRegisterInfo::isPhysicalRegister(OtherReg) in collectHintInfo()
2839 ? OtherReg in collectHintInfo()
2840 : VRM->getPhys(OtherReg); in collectHintInfo()
2842 Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg, in collectHintInfo()
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| D | RegisterCoalescer.cpp | 3354 unsigned OtherReg, OtherSubReg, OtherSrcReg, OtherSrcSubReg; in applyTerminalRule() local
3355 isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg, in applyTerminalRule()
3357 if (OtherReg == SrcReg) in applyTerminalRule()
3358 OtherReg = OtherSrcReg; in applyTerminalRule()
3360 if (TargetRegisterInfo::isPhysicalRegister(OtherReg) || in applyTerminalRule()
3361 isTerminalReg(OtherReg, MI, MRI)) in applyTerminalRule()
3364 if (LIS->getInterval(OtherReg).overlaps(DstLI)) { in applyTerminalRule()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 579 unsigned OtherReg = Hint.second; in UpdateRegAllocHint() local
580 Hint = MRI->getRegAllocationHint(OtherReg); in UpdateRegAllocHint()
583 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in UpdateRegAllocHint()
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