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Searched refs:OutputCount (Results 1 – 18 of 18) sorted by relevance

/external/v8/src/compiler/
Dregister-allocator-verifier.cc18 return instr->InputCount() + instr->OutputCount() + instr->TempCount(); in OperandCount()
77 for (size_t i = 0; i < instr->OutputCount(); ++i, ++count) { in RegisterAllocatorVerifier()
137 for (size_t i = 0; i < instr->OutputCount(); ++i, ++count) { in VerifyAssignment()
524 for (size_t i = 0; i < instr->OutputCount(); ++i, ++count) { in VerifyGapMoves()
Dinstruction.h804 size_t OutputCount() const { return OutputCountField::decode(bit_field_); } in OutputCount() function
806 DCHECK(i < OutputCount()); in OutputAt()
810 DCHECK(i < OutputCount()); in OutputAt()
814 bool HasOutput() const { return OutputCount() > 0; } in HasOutput()
821 return &operands_[OutputCount() + i]; in InputAt()
825 return &operands_[OutputCount() + i]; in InputAt()
831 return &operands_[OutputCount() + InputCount() + i]; in TempAt()
835 return &operands_[OutputCount() + InputCount() + i]; in TempAt()
Dmove-optimizer.cc181 for (size_t i = 0; i < instruction->OutputCount(); ++i) { in RemoveClobberedDestinations()
232 for (size_t i = 0; i < from->OutputCount(); ++i) { in MigrateMoves()
394 if (last_instr->OutputCount() != 0) return; in OptimizeMerge()
Dinstruction.cc540 if (instr.OutputCount() > 1) os << "("; in operator <<()
541 for (size_t i = 0; i < instr.OutputCount(); i++) { in operator <<()
547 if (instr.OutputCount() > 1) os << ") = "; in operator <<()
548 if (instr.OutputCount() == 1) os << " = "; in operator <<()
804 for (size_t i = 0; i < instruction->OutputCount(); ++i) { in ValidateSSA()
Dinstruction-scheduler.h187 return (instr->arch_opcode() == kArchNop) && (instr->OutputCount() == 1) && in IsFixedRegisterParameter()
Dinstruction-scheduler.cc191 for (size_t i = 0; i < instr->OutputCount(); ++i) { in AddInstruction()
Dregister-allocator.cc1656 for (size_t i = 0; i < last_instruction->OutputCount(); i++) { in MeetRegisterConstraintsForLastInstructionInBlock()
1707 for (size_t i = 0; i < first->OutputCount(); i++) { in MeetConstraintsAfter()
1773 for (size_t i = 0; i < second->OutputCount(); i++) { in MeetConstraintsBefore()
2056 for (size_t i = 0; i < instr->OutputCount(); i++) { in ProcessInstructions()
Dcode-generator.cc984 index < index_from_top + iter->instruction()->OutputCount()) { in TranslateFrameStateDescriptorOperands()
Dpipeline.cc2452 instr->InputCount(), instr->OutputCount()); in VerifyGeneratedCodeIsIdempotent()
/external/v8/src/compiler/s390/
Dcode-generator-s390.cc31 size_t OutputCount() { return instr_->OutputCount(); } in OutputCount() function in v8::internal::compiler::S390OperandConverter
133 return instr->OutputCount() > 0 && instr->OutputAt(index)->IsRegister(); in HasRegisterOutput()
1746 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1758 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1772 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
2303 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2308 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2318 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2324 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2352 if (i.OutputCount() > 1) { in AssembleArchInstruction()
[all …]
/external/v8/src/compiler/ppc/
Dcode-generator-ppc.cc33 size_t OutputCount() { return instr_->OutputCount(); } in OutputCount() function in v8::internal::compiler::PPCOperandConverter
1291 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1303 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1317 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1812 (opcode == kPPC_DoubleToInt64 && i.OutputCount() > 1); in AssembleArchInstruction()
1844 bool check_conversion = (i.OutputCount() > 1); in AssembleArchInstruction()
2221 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
2222 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc60 size_t OutputCount() { return instr_->OutputCount(); } in OutputCount() function in v8::internal::compiler::Arm64OperandConverter
1423 if (i.OutputCount() > 1) { in AssembleArchInstruction()
1436 if (i.OutputCount() > 1) { in AssembleArchInstruction()
1445 if (i.OutputCount() > 1) { in AssembleArchInstruction()
1454 if (i.OutputCount() > 1) { in AssembleArchInstruction()
2297 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
2298 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/external/v8/src/compiler/x64/
Dcode-generator-x64.cc1501 if (instr->OutputCount() > 1) { in AssembleArchInstruction()
1530 if (instr->OutputCount() > 1) { in AssembleArchInstruction()
1555 if (instr->OutputCount() > 1) __ Set(i.OutputRegister(1), 0); in AssembleArchInstruction()
1561 if (instr->OutputCount() > 1) __ Set(i.OutputRegister(1), 1); in AssembleArchInstruction()
1567 if (instr->OutputCount() > 1) __ Set(i.OutputRegister(1), 0); in AssembleArchInstruction()
1573 if (instr->OutputCount() > 1) __ Set(i.OutputRegister(1), 1); in AssembleArchInstruction()
2973 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
2974 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/external/v8/src/compiler/mips64/
Dinstruction-scheduler-mips64.cc1522 return TruncLSLatency(instr->OutputCount() > 1); in GetInstructionLatency()
1524 return TruncLDLatency(instr->OutputCount() > 1); in GetInstructionLatency()
Dcode-generator-mips64.cc1553 bool load_status = instr->OutputCount() > 1; in AssembleArchInstruction()
1581 bool load_status = instr->OutputCount() > 1; in AssembleArchInstruction()
1620 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
1627 Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; in AssembleArchInstruction()
3247 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
3248 Register result = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/external/v8/src/compiler/mips/
Dcode-generator-mips.cc1043 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1056 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1069 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
3009 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
3010 Register result = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc1254 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1266 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
1278 instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0); in AssembleArchInstruction()
2950 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
2951 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()
/external/v8/src/compiler/ia32/
Dcode-generator-ia32.cc4004 DCHECK_NE(0u, instr->OutputCount()); in AssembleArchBoolean()
4005 Register reg = i.OutputRegister(instr->OutputCount() - 1); in AssembleArchBoolean()