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/external/speex/ti/speex_C54_test/
Dspeex_C54_test.cmd42 /* PAGE 0: P_DARAM03: origin = 0x80, len = 0x7f00*/
43 PAGE 0: P_DARAM03: origin = 0x5000, len = 0x2f80
44 PAGE 0: VECT: origin = 0x7f80, len = 0x80
45 PAGE 0: P_DARAM47: origin = 0x18000, len = 0x8000
46 PAGE 0: SARAM03: origin = 0x28000, len = 0x8000
47 PAGE 0: SARAM47: origin = 0x38000, len = 0x8000
49 PAGE 1: USERREGS: origin = 0x60, len = 0x1a
50 PAGE 1: BIOSREGS: origin = 0x7c, len = 0x4
51 PAGE 1: CSLREGS: origin = 0x7a, len = 0x2
58 .vectors: {} > VECT PAGE 0
[all …]
/external/jemalloc/test/unit/
Dpages.c9 pages = pages_map(NULL, PAGE, &commit); in TEST_BEGIN()
12 assert_false(pages_huge(pages, PAGE), in TEST_BEGIN()
14 assert_false(pages_nohuge(pages, PAGE), in TEST_BEGIN()
17 pages_unmap(pages, PAGE); in TEST_BEGIN()
Drun_quantize.c66 run_size = cache_oblivious ? lrun_size + PAGE : lrun_size; in TEST_BEGIN()
79 - PAGE), "Floor should be a precise size"); in TEST_BEGIN()
89 ceil_prev = run_quantize_ceil(run_size + PAGE); in TEST_BEGIN()
/external/jemalloc_new/test/unit/
Drtree.c76 assert_ptr_null(rtree_extent_read(tsdn, rtree, &rtree_ctx, PAGE, in TEST_BEGIN()
101 assert_false(rtree_write(tsdn, rtree, &rtree_ctx, PAGE, &extent_a, in TEST_BEGIN()
104 rtree_szind_slab_update(tsdn, rtree, &rtree_ctx, PAGE, in TEST_BEGIN()
106 assert_ptr_eq(rtree_extent_read(tsdn, rtree, &rtree_ctx, PAGE, true), in TEST_BEGIN()
124 uintptr_t keys[] = {PAGE, PAGE + 1, in TEST_BEGIN()
125 PAGE + (((uintptr_t)1) << LG_PAGE) - 1}; in TEST_BEGIN()
Dextent_quantize.c66 extent_size = cache_oblivious ? lextent_size + PAGE : in TEST_BEGIN()
82 extent_size_quantize_floor(extent_size - PAGE), in TEST_BEGIN()
95 PAGE); in TEST_BEGIN()
Dpages.c8 alloc_size = HUGEPAGE * 2 - PAGE; in TEST_BEGIN()
10 pages = pages_map(NULL, alloc_size, PAGE, &commit); in TEST_BEGIN()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dglobal-merge-ignore-single-use-minsize.ll14 ; CHECK-NEXT: adrp x8, [[SET:__MergedGlobals]]@PAGE
28 ; CHECK-NEXT: adrp x8, _m2@PAGE
29 ; CHECK-NEXT: adrp x9, _n2@PAGE
47 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE+8
60 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE+8
61 ; CHECK-NEXT: adrp x9, _n4@PAGE
Dglobal-merge-group-by-use.ll16 ; CHECK-NEXT: adrp x8, [[SET1:__MergedGlobals.[0-9]*]]@PAGE
31 ; CHECK-NEXT: adrp x8, [[SET2:__MergedGlobals.[0-9]*]]@PAGE
51 ; CHECK-NEXT: adrp x8, _m3@PAGE
52 ; CHECK-NEXT: adrp x9, [[SET3:__MergedGlobals[0-9]*]]@PAGE
66 ; CHECK-NEXT: adrp x8, [[SET3]]@PAGE
82 ; CHECK-NEXT: adrp x8, _o5@PAGE
Darm64-fp-imm.ll7 ; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE
17 ; CHECK: adrp x[[REG:[0-9]+]], lCPI1_0@PAGE
28 ; CHECK: adrp x[[REG:[0-9]+]], lCPI2_0@PAGE
Darm64-fast-isel-intrinsic.ll8 ; ARM64: adrp x8, _message@PAGE
24 ; ARM64: adrp x8, _message@PAGE
38 ; ARM64: adrp x8, _message@PAGE
52 ; ARM64: adrp x9, _message@PAGE
69 ; ARM64: adrp x9, _message@PAGE
86 ; ARM64: adrp x9, _message@PAGE
103 ; ARM64: adrp x9, _message@PAGE
122 ; ARM64: adrp x9, _message@PAGE
Darm64-2012-05-07-MemcpyAlignBug.ll9 ; CHECK: adrp x[[PAGE:[0-9]+]], {{l_b@PAGE|.Lb}}
10 ; CHECK: add x[[ADDR:[0-9]+]], x[[PAGE]], {{l_b@PAGEOFF|:lo12:.Lb}}
Dglobal-merge-ignore-single-use.ll14 ; CHECK-NEXT: adrp x8, [[SET:__MergedGlobals]]@PAGE
28 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE
41 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE+12
54 ; CHECK-NEXT: adrp x8, _o2@PAGE
Darm64-promote-const.ll14 ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], __PromotedConst@PAGE
24 ; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
27 ; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
29 ; REGULAR: adrp [[PAGEADDR2:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE
31 ; REGULAR: adrp [[PAGEADDR3:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE
43 ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst.[0-9]+]]@PAGE
54 ; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
/external/llvm/test/CodeGen/AArch64/
Dglobal-merge-ignore-single-use-minsize.ll14 ; CHECK-NEXT: adrp x8, [[SET:l__MergedGlobals]]@PAGE
28 ; CHECK-NEXT: adrp x8, _m2@PAGE
29 ; CHECK-NEXT: adrp x9, _n2@PAGE
47 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE
60 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE
62 ; CHECK-NEXT: adrp x9, _n4@PAGE
Dglobal-merge-group-by-use.ll15 ; CHECK-NEXT: adrp x8, [[SET1:l__MergedGlobals.[0-9]*]]@PAGE
30 ; CHECK-NEXT: adrp x8, [[SET2:l__MergedGlobals.[0-9]*]]@PAGE
50 ; CHECK-NEXT: adrp x8, _m3@PAGE
51 ; CHECK-NEXT: adrp x9, [[SET3:l__MergedGlobals[0-9]*]]@PAGE
65 ; CHECK-NEXT: adrp x8, [[SET3]]@PAGE
81 ; CHECK-NEXT: adrp x8, _o5@PAGE
Darm64-fp-imm.ll7 ; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE
17 ; CHECK: adrp x[[REG:[0-9]+]], lCPI1_0@PAGE
28 ; CHECK: adrp x[[REG:[0-9]+]], lCPI2_0@PAGE
Darm64-fast-isel-intrinsic.ll8 ; ARM64: adrp x8, _message@PAGE
24 ; ARM64: adrp x8, _message@PAGE
38 ; ARM64: adrp x8, _message@PAGE
52 ; ARM64: adrp x9, _message@PAGE
69 ; ARM64: adrp x9, _message@PAGE
86 ; ARM64: adrp x9, _message@PAGE
103 ; ARM64: adrp x9, _message@PAGE
122 ; ARM64: adrp x9, _message@PAGE
Darm64-2012-05-07-MemcpyAlignBug.ll9 ; CHECK: adrp x[[PAGE:[0-9]+]], {{l_b@PAGE|.Lb}}
10 ; CHECK: add x[[ADDR:[0-9]+]], x[[PAGE]], {{l_b@PAGEOFF|:lo12:.Lb}}
Dglobal-merge-ignore-single-use.ll13 ; CHECK-NEXT: adrp x8, [[SET:l__MergedGlobals]]@PAGE
27 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE
40 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE
53 ; CHECK-NEXT: adrp x8, _o2@PAGE
/external/jemalloc_new/src/
Dpages.c120 void *new_addr = os_pages_map(ret, size, PAGE, commit); in os_pages_trim()
194 assert(alignment >= PAGE); in pages_map()
578 if (os_page > PAGE) { in pages_boot()
615 void *madv_free_page = os_pages_map(NULL, PAGE, PAGE, &committed); in pages_boot()
620 if (pages_purge_lazy(madv_free_page, PAGE)) { in pages_boot()
623 os_pages_unmap(madv_free_page, PAGE); in pages_boot()
/external/jemalloc_new/include/jemalloc/internal/
Dsz.h44 PAGE
76 return LARGE_MAXCLASS + PAGE; in sz_pind2sz_compute()
111 return LARGE_MAXCLASS + PAGE; in sz_psz2u()
268 if (size <= SMALL_MAXCLASS && alignment < PAGE) { in sz_sa2u()
310 if (usize + sz_large_pad + PAGE_CEILING(alignment) - PAGE < usize) { in sz_sa2u()
/external/syzkaller/pkg/report/testdata/fuchsia/report/
D03 gfxconsole: rows <PAGE FAULT> Instruction Pointer = 0x10:0xffffffff801a41a7
4 48<PAGE FAULT> Stack Pointer = 0x18:0xffffff9951906e90
5 , columns <PAGE FAULT> Fault Linear Address = 0xb0
6 113<PAGE FAULT> Error Code Value = 0x0
7 , extray <PAGE FAULT> Error Code Type = supervisor read data, page not present
/external/llvm/test/MC/AArch64/
Darm64-arm64-fixup.s9 ; CHECK: adrp x3, _printf@PAGE ; encoding: [0x03'A',A,A,0x90'A']
10 ; CHECK: fixup A - offset: 0, value: _printf@PAGE, kind: fixup_aarch64_pcrel_adrp_imm21
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-arm64-fixup.s9 ; CHECK: adrp x3, _printf@PAGE ; encoding: [0x03'A',A,A,0x90'A']
10 ; CHECK: fixup A - offset: 0, value: _printf@PAGE, kind: fixup_aarch64_pcrel_adrp_imm21
/external/autotest/client/cros/cellular/
Dforward_8960_screen24 PAGE=""" variable
101 self.wfile.write(PAGE % {'ssh_tunnel_port': ssh_tunnel_port,

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