Home
last modified time | relevance | path

Searched refs:PBS_RX_PHY_REG (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_centralization.c626 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx()
636 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx()
650 PBS_RX_PHY_REG(effective_cs, 4), in ddr3_tip_special_rx()
657 PBS_RX_PHY_REG(effective_cs, 4), in ddr3_tip_special_rx()
663 PBS_RX_PHY_REG(effective_cs, 5), in ddr3_tip_special_rx()
670 PBS_RX_PHY_REG(effective_cs, 5), in ddr3_tip_special_rx()
Dddr3_training_pbs.c773 PBS_RX_PHY_REG(effective_cs, 0) : in ddr3_tip_pbs()
941 PBS_RX_PHY_REG(cs_num, 0) : in ddr3_tip_print_pbs_result()
991 PBS_RX_PHY_REG(effective_cs, 0) : in ddr3_tip_clean_pbs_result()
Dmv_ddr_regs.h436 #define PBS_RX_PHY_REG(cs, bit) (PBS_RX_PHY_BASE + (cs) * 0x10 + (bit)) macro
Dddr3_training.c2049 PBS_RX_PHY_REG(effective_cs, DQSP_PAD), 0)); in ddr3_tip_ddr3_reset_phy_regs()
2057 PBS_RX_PHY_REG(effective_cs, DQSN_PAD), 0)); in ddr3_tip_ddr3_reset_phy_regs()