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1 /*
2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3  * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8 */
9 
10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
11 #define _DT_BINDINGS_CLOCK_EXYNOS7_H
12 
13 /* TOPC */
14 #define DOUT_ACLK_PERIS			1
15 #define DOUT_SCLK_BUS0_PLL		2
16 #define DOUT_SCLK_BUS1_PLL		3
17 #define DOUT_SCLK_CC_PLL		4
18 #define DOUT_SCLK_MFC_PLL		5
19 #define DOUT_ACLK_CCORE_133		6
20 #define DOUT_ACLK_MSCL_532		7
21 #define ACLK_MSCL_532			8
22 #define DOUT_SCLK_AUD_PLL		9
23 #define FOUT_AUD_PLL			10
24 #define SCLK_AUD_PLL			11
25 #define SCLK_MFC_PLL_B			12
26 #define SCLK_MFC_PLL_A			13
27 #define SCLK_BUS1_PLL_B			14
28 #define SCLK_BUS1_PLL_A			15
29 #define SCLK_BUS0_PLL_B			16
30 #define SCLK_BUS0_PLL_A			17
31 #define SCLK_CC_PLL_B			18
32 #define SCLK_CC_PLL_A			19
33 #define ACLK_CCORE_133			20
34 #define ACLK_PERIS_66			21
35 #define TOPC_NR_CLK			22
36 
37 /* TOP0 */
38 #define DOUT_ACLK_PERIC1		1
39 #define DOUT_ACLK_PERIC0		2
40 #define CLK_SCLK_UART0			3
41 #define CLK_SCLK_UART1			4
42 #define CLK_SCLK_UART2			5
43 #define CLK_SCLK_UART3			6
44 #define CLK_SCLK_SPI0			7
45 #define CLK_SCLK_SPI1			8
46 #define CLK_SCLK_SPI2			9
47 #define CLK_SCLK_SPI3			10
48 #define CLK_SCLK_SPI4			11
49 #define CLK_SCLK_SPDIF			12
50 #define CLK_SCLK_PCM1			13
51 #define CLK_SCLK_I2S1			14
52 #define CLK_ACLK_PERIC0_66		15
53 #define CLK_ACLK_PERIC1_66		16
54 #define TOP0_NR_CLK			17
55 
56 /* TOP1 */
57 #define DOUT_ACLK_FSYS1_200		1
58 #define DOUT_ACLK_FSYS0_200		2
59 #define DOUT_SCLK_MMC2			3
60 #define DOUT_SCLK_MMC1			4
61 #define DOUT_SCLK_MMC0			5
62 #define CLK_SCLK_MMC2			6
63 #define CLK_SCLK_MMC1			7
64 #define CLK_SCLK_MMC0			8
65 #define CLK_ACLK_FSYS0_200		9
66 #define CLK_ACLK_FSYS1_200		10
67 #define CLK_SCLK_PHY_FSYS1		11
68 #define CLK_SCLK_PHY_FSYS1_26M		12
69 #define MOUT_SCLK_UFSUNIPRO20		13
70 #define DOUT_SCLK_UFSUNIPRO20		14
71 #define CLK_SCLK_UFSUNIPRO20		15
72 #define DOUT_SCLK_PHY_FSYS1		16
73 #define DOUT_SCLK_PHY_FSYS1_26M		17
74 #define TOP1_NR_CLK			18
75 
76 /* CCORE */
77 #define PCLK_RTC			1
78 #define CCORE_NR_CLK			2
79 
80 /* PERIC0 */
81 #define PCLK_UART0			1
82 #define SCLK_UART0			2
83 #define PCLK_HSI2C0			3
84 #define PCLK_HSI2C1			4
85 #define PCLK_HSI2C4			5
86 #define PCLK_HSI2C5			6
87 #define PCLK_HSI2C9			7
88 #define PCLK_HSI2C10			8
89 #define PCLK_HSI2C11			9
90 #define PCLK_PWM			10
91 #define SCLK_PWM			11
92 #define PCLK_ADCIF			12
93 #define PERIC0_NR_CLK			13
94 
95 /* PERIC1 */
96 #define PCLK_UART1			1
97 #define PCLK_UART2			2
98 #define PCLK_UART3			3
99 #define SCLK_UART1			4
100 #define SCLK_UART2			5
101 #define SCLK_UART3			6
102 #define PCLK_HSI2C2			7
103 #define PCLK_HSI2C3			8
104 #define PCLK_HSI2C6			9
105 #define PCLK_HSI2C7			10
106 #define PCLK_HSI2C8			11
107 #define PCLK_SPI0			12
108 #define PCLK_SPI1			13
109 #define PCLK_SPI2			14
110 #define PCLK_SPI3			15
111 #define PCLK_SPI4			16
112 #define SCLK_SPI0			17
113 #define SCLK_SPI1			18
114 #define SCLK_SPI2			19
115 #define SCLK_SPI3			20
116 #define SCLK_SPI4			21
117 #define PCLK_I2S1			22
118 #define PCLK_PCM1			23
119 #define PCLK_SPDIF			24
120 #define SCLK_I2S1			25
121 #define SCLK_PCM1			26
122 #define SCLK_SPDIF			27
123 #define PERIC1_NR_CLK			28
124 
125 /* PERIS */
126 #define PCLK_CHIPID			1
127 #define SCLK_CHIPID			2
128 #define PCLK_WDT			3
129 #define PCLK_TMU			4
130 #define SCLK_TMU			5
131 #define PERIS_NR_CLK			6
132 
133 /* FSYS0 */
134 #define ACLK_MMC2			1
135 #define ACLK_AXIUS_USBDRD30X_FSYS0X	2
136 #define ACLK_USBDRD300			3
137 #define SCLK_USBDRD300_SUSPENDCLK	4
138 #define SCLK_USBDRD300_REFCLK		5
139 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
140 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
141 #define OSCCLK_PHY_CLKOUT_USB30_PHY		8
142 #define ACLK_PDMA0			9
143 #define ACLK_PDMA1			10
144 #define FSYS0_NR_CLK			11
145 
146 /* FSYS1 */
147 #define ACLK_MMC1			1
148 #define ACLK_MMC0			2
149 #define PHYCLK_UFS20_TX0_SYMBOL		3
150 #define PHYCLK_UFS20_RX0_SYMBOL		4
151 #define PHYCLK_UFS20_RX1_SYMBOL		5
152 #define ACLK_UFS20_LINK			6
153 #define SCLK_UFSUNIPRO20_USER		7
154 #define PHYCLK_UFS20_RX1_SYMBOL_USER	8
155 #define PHYCLK_UFS20_RX0_SYMBOL_USER	9
156 #define PHYCLK_UFS20_TX0_SYMBOL_USER	10
157 #define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
158 #define SCLK_COMBO_PHY_EMBEDDED_26M	12
159 #define DOUT_PCLK_FSYS1			13
160 #define PCLK_GPIO_FSYS1			14
161 #define MOUT_FSYS1_PHYCLK_SEL1		15
162 #define FSYS1_NR_CLK			16
163 
164 /* MSCL */
165 #define USERMUX_ACLK_MSCL_532		1
166 #define DOUT_PCLK_MSCL			2
167 #define ACLK_MSCL_0			3
168 #define ACLK_MSCL_1			4
169 #define ACLK_JPEG			5
170 #define ACLK_G2D			6
171 #define ACLK_LH_ASYNC_SI_MSCL_0		7
172 #define ACLK_LH_ASYNC_SI_MSCL_1		8
173 #define ACLK_AXI2ACEL_BRIDGE		9
174 #define ACLK_XIU_MSCLX_0		10
175 #define ACLK_XIU_MSCLX_1		11
176 #define ACLK_QE_MSCL_0			12
177 #define ACLK_QE_MSCL_1			13
178 #define ACLK_QE_JPEG			14
179 #define ACLK_QE_G2D			15
180 #define ACLK_PPMU_MSCL_0		16
181 #define ACLK_PPMU_MSCL_1		17
182 #define ACLK_MSCLNP_133			18
183 #define ACLK_AHB2APB_MSCL0P		19
184 #define ACLK_AHB2APB_MSCL1P		20
185 
186 #define PCLK_MSCL_0			21
187 #define PCLK_MSCL_1			22
188 #define PCLK_JPEG			23
189 #define PCLK_G2D			24
190 #define PCLK_QE_MSCL_0			25
191 #define PCLK_QE_MSCL_1			26
192 #define PCLK_QE_JPEG			27
193 #define PCLK_QE_G2D			28
194 #define PCLK_PPMU_MSCL_0		29
195 #define PCLK_PPMU_MSCL_1		30
196 #define PCLK_AXI2ACEL_BRIDGE		31
197 #define PCLK_PMU_MSCL			32
198 #define MSCL_NR_CLK			33
199 
200 /* AUD */
201 #define SCLK_I2S			1
202 #define SCLK_PCM			2
203 #define PCLK_I2S			3
204 #define PCLK_PCM			4
205 #define ACLK_ADMA			5
206 #define AUD_NR_CLK			6
207 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
208