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Searched refs:PERIPH_REG (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra114/
Dclock.c584 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
586 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
605 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
607 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c564 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
566 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
585 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
587 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
/external/u-boot/arch/arm/include/asm/arch-tegra20/
Dclock-tables.h172 #define PERIPH_REG(id) ((id) >> 5) macro
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c730 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
732 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
753 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
755 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
/external/u-boot/arch/arm/include/asm/arch-tegra114/
Dclock-tables.h378 #define PERIPH_REG(id) \ macro
/external/u-boot/arch/arm/include/asm/arch-tegra30/
Dclock-tables.h358 #define PERIPH_REG(id) \ macro
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c820 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
822 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
846 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
848 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
/external/u-boot/arch/arm/include/asm/arch-tegra124/
Dclock-tables.h483 #define PERIPH_REG(id) \ macro
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c511 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
528 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
/external/u-boot/arch/arm/include/asm/arch-tegra210/
Dclock-tables.h553 #define PERIPH_REG(id) \ macro