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Searched refs:PHY_CON0_RESET_VAL (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Ddmc_init_ddr3.c139 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init()
149 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init()
170 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init()
691 writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
692 writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
Dexynos5_setup.h254 #define PHY_CON0_RESET_VAL 0x17020a40 macro