Searched refs:PINSRW (Results 1 – 14 of 14) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.h | 174 PINSRW, MMX_PINSRW, enumerator
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| D | X86InstrFragmentsSIMD.td | 81 def X86pinsrw : SDNode<"X86ISD::PINSRW",
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| D | X86ISelLowering.cpp | 7014 Opc = X86ISD::PINSRW; in LowerINSERT_VECTOR_ELT_SSE4()
7091 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); in LowerINSERT_VECTOR_ELT()
10658 case X86ISD::PINSRW: return "X86ISD::PINSRW"; in getTargetNodeName()
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| D | X86InstrSSE.td | 4021 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
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| D | X86GenDAGISel.inc | 43548 /*SwitchOpcode*/ 116, TARGET_VAL(X86ISD::PINSRW),// ->91089
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 177 PINSRW, MMX_PINSRW, enumerator
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| D | X86InstrFragmentsSIMD.td | 108 def X86pinsrw : SDNode<"X86ISD::PINSRW",
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| D | X86ISelLowering.cpp | 12624 Opc = X86ISD::PINSRW; in LowerINSERT_VECTOR_ELT()
12684 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); in LowerINSERT_VECTOR_ELT()
22123 case X86ISD::PINSRW: return "X86ISD::PINSRW"; in getTargetNodeName()
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| D | X86InstrSSE.td | 4569 defm PINSRW : sse2_pinsrw, PD;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 188 PINSRW, enumerator
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| D | X86InstrFragmentsSIMD.td | 94 def X86pinsrw : SDNode<"X86ISD::PINSRW",
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| D | X86ISelLowering.cpp | 6237 case X86ISD::PINSRW: { in getFauxShuffleMask()
15579 Opc = X86ISD::PINSRW; in LowerINSERT_VECTOR_ELT()
25942 case X86ISD::PINSRW: return "X86ISD::PINSRW"; in getTargetNodeName()
34351 (N->getOpcode() == X86ISD::PINSRW && in combineVectorInsert()
39694 case X86ISD::PINSRW: return combineVectorInsert(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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| D | X86InstrSSE.td | 3890 defm PINSRW : sse2_pinsrw, PD;
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| /external/syzkaller/pkg/ifuzz/gen/ |
| D | all-enc-instructions.txt | 10018 ICLASS : PINSRW
10078 ICLASS : PINSRW
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