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Searched refs:PIPE_CONTROL_CACHE_FLUSH_BITS (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c232 (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) && in brw_emit_pipe_control_flush()
245 brw_emit_end_of_pipe_sync(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS)); in brw_emit_pipe_control_flush()
246 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL); in brw_emit_pipe_control_flush()
Dgen8_multisample_state.c67 PIPE_CONTROL_CACHE_FLUSH_BITS | in gen10_emit_wa_lri_to_cache_mode_zero()
Dbrw_pipe_control.h63 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ macro