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Searched refs:PIPE_CONTROL_CACHE_INVALIDATE_BITS (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen8_multisample_state.c68 PIPE_CONTROL_CACHE_INVALIDATE_BITS); in gen10_emit_wa_lri_to_cache_mode_zero()
Dbrw_pipe_control.h67 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ macro
Dbrw_pipe_control.c233 (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { in brw_emit_pipe_control_flush()