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Searched refs:PIPE_CONTROL_CS_STALL (Results 1 – 15 of 15) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c59 if ((*flags & PIPE_CONTROL_CS_STALL) != 0 && (*flags & wa_bits) == 0) in gen8_add_cs_stall_workaround_bits()
77 if (flags & PIPE_CONTROL_CS_STALL) { in gen7_cs_stall_every_four_pipe_controls()
86 return PIPE_CONTROL_CS_STALL; in gen7_cs_stall_every_four_pipe_controls()
246 flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL); in brw_emit_pipe_control_flush()
358 PIPE_CONTROL_CS_STALL, in gen10_emit_isp_disable()
375 PIPE_CONTROL_CS_STALL in gen7_emit_cs_stall_flush()
421 PIPE_CONTROL_CS_STALL | in brw_emit_post_sync_nonzero_flush()
481 flags | PIPE_CONTROL_CS_STALL | in brw_emit_end_of_pipe_sync()
558 PIPE_CONTROL_CS_STALL; in brw_emit_mi_flush()
Dbrw_queryobj.c92 PIPE_CONTROL_CS_STALL | in brw_write_timestamp()
99 flags |= PIPE_CONTROL_CS_STALL; in brw_write_timestamp()
115 flags |= PIPE_CONTROL_CS_STALL; in brw_write_depth_count()
Dgen7_l3_state.c90 PIPE_CONTROL_CS_STALL); in setup_l3_config()
119 PIPE_CONTROL_CS_STALL); in setup_l3_config()
Dgen8_multisample_state.c42 PIPE_CONTROL_CS_STALL | in gen10_emit_wa_cs_stall_flush()
Dbrw_pipe_control.h37 #define PIPE_CONTROL_CS_STALL (1 << 20) macro
Dbrw_blorp.c436 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | in brw_blorp_copy_miptrees()
446 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | in brw_blorp_copy_miptrees()
1582 PIPE_CONTROL_CS_STALL); in intel_hiz_exec()
1607 PIPE_CONTROL_CS_STALL); in intel_hiz_exec()
1640 PIPE_CONTROL_CS_STALL); in intel_hiz_exec()
Dgen8_depth_state.c329 PIPE_CONTROL_CS_STALL | in gen8_write_pma_stall_bits()
Dbrw_program.c282 PIPE_CONTROL_CS_STALL); in brw_memory_barrier()
325 PIPE_CONTROL_CS_STALL); in brw_blend_barrier()
Dintel_tex.c315 PIPE_CONTROL_CS_STALL); in intel_texture_barrier()
Dgen6_queryobj.c70 flags |= PIPE_CONTROL_CS_STALL; in set_query_availability()
Dhsw_queryobj.c295 PIPE_CONTROL_CS_STALL | in hsw_result_to_gpr0()
Dbrw_misc_state.c466 PIPE_CONTROL_CS_STALL); in brw_emit_select_pipeline()
Dintel_fbo.c1005 PIPE_CONTROL_CS_STALL); in flush_depth_and_render_caches()
Dintel_batchbuffer.c768 PIPE_CONTROL_CS_STALL); in brw_finish_batch()
DgenX_state_upload.c4202 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);