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Searched refs:PIPE_CONTROL_RENDER_TARGET_FLUSH (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c47 uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH | in gen8_add_cs_stall_workaround_bits()
102 if (*flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) { in gen10_add_rcpfe_workaround_bits()
178 (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) { in brw_emit_pipe_control()
550 int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; in brw_emit_mi_flush()
Dbrw_pipe_control.h47 #define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12) macro
65 PIPE_CONTROL_RENDER_TARGET_FLUSH)
Dbrw_program.c300 PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_memory_barrier()
304 PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_memory_barrier()
310 bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH; in brw_memory_barrier()
324 PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_blend_barrier()
330 PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_blend_barrier()
Dbrw_blorp.c1263 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in do_single_blorp_clear()
1272 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in do_single_blorp_clear()
1490 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_blorp_resolve_color()
1501 brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); in brw_blorp_resolve_color()
1580 PIPE_CONTROL_RENDER_TARGET_FLUSH | in intel_hiz_exec()
Dbrw_misc_state.c462 PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_emit_select_pipeline()
631 PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_upload_state_base_address()
Dgen8_depth_state.c327 brw->stencil_write_enabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0; in gen8_write_pma_stall_bits()
Dintel_tex.c314 PIPE_CONTROL_RENDER_TARGET_FLUSH | in intel_texture_barrier()
Dintel_fbo.c1004 PIPE_CONTROL_RENDER_TARGET_FLUSH | in flush_depth_and_render_caches()
Dintel_batchbuffer.c767 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_finish_batch()