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Searched refs:PIPE_CONTROL_STATE_CACHE_INVALIDATE (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.h57 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2) macro
68 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
Dbrw_misc_state.c471 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in brw_emit_select_pipeline()
735 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in brw_upload_state_base_address()
Dgen7_l3_state.c110 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in setup_l3_config()
DgenX_state_upload.c2160 PIPE_CONTROL_STATE_CACHE_INVALIDATE);