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Searched refs:PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.h49 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1 << 10) /* GM45+ only */ macro
69 PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
Dbrw_program.c291 bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_memory_barrier()
295 bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; in brw_memory_barrier()
299 bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_memory_barrier()
303 bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_memory_barrier()
327 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in brw_blend_barrier()
Dbrw_misc_state.c469 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_emit_select_pipeline()
736 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in brw_upload_state_base_address()
Dbrw_pipe_control.c557 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in brw_emit_mi_flush()
Dgen7_l3_state.c107 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in setup_l3_config()
Dintel_tex.c318 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in intel_texture_barrier()
Dbrw_blorp.c437 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in brw_blorp_copy_miptrees()
447 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in brw_blorp_copy_miptrees()
Dintel_fbo.c1008 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | in flush_depth_and_render_caches()