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Searched refs:PL5 (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/arch/arm/dts/
Dsun8i-a33-inet-d978-rev2.dts59 gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
83 allwinner,pins = "PL5";
Dsunxi-libretech-all-h3-cc.dtsi92 gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
Dsun6i-a31s-sinovoip-bpi-m2.dts141 interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */
Dsun9i-a80-cx-a99.dts135 <&r_pio 0 5 /* no flag support */ 0>; /* PL5 */
/external/u-boot/configs/
Dh8_homlet_v2_defconfig8 CONFIG_USB0_VBUS_PIN="PL5"
/external/python/cpython2/Lib/plat-unixware7/
DIN.py408 PL5 = 5 variable
414 PLDISK = PL5
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart3.csv18568 ,"US","PL5","Liberty","Liberty","PA","-----6--","RL","0901",,"4019N 07951W",
D2013-1_UNLOCODE_CodeListPart1.csv40038 "X","FR","PL5","Port Lay","Port Lay",,"1-------","XX","1301",,"4738N 00328W",""