Searched refs:PLL1 (Results 1 – 7 of 7) sorted by relevance
32 ; This section allows setting up the PLL1. Usually this will57 ; This section can be used to configure the PLL1 and the EMIF3a registers155 ; This section allows setting up the PLL1. Usually this will165 ; This section can be used to configure the PLL1 and the EMIF3a registers182 ; This section can be used to configure the PLL1 and the EMIF3a registers
176 #define PLL1 163 macro
54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
561 DUMP_REG(PLL1); in dump_sor_reg()720 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | in tegra_dc_sor_enable_dp()
251 #define PLL1 0x18 macro
52 PLL children node for PLL1 to PLL4 : (see ref manual for details)
217 * PLL1 is listed twice here.