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Searched refs:PLLE_BASE_MDIV (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c663 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
745 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
746 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c947 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
996 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
999 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c1132 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
1185 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
1188 value |= PLLE_BASE_MDIV(2); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c634 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro