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Searched refs:PLLE_BASE_NDIV (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c662 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) macro
742 value &= ~PLLE_BASE_NDIV(0xff); in tegra_plle_enable()
743 value |= PLLE_BASE_NDIV(n); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c946 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) macro
995 value &= ~PLLE_BASE_NDIV(0xff); in tegra_plle_enable()
998 value |= PLLE_BASE_NDIV(n); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c1131 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) macro
1184 value &= ~PLLE_BASE_NDIV(0xff); in tegra_plle_enable()
1187 value |= PLLE_BASE_NDIV(0x7d); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c633 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) macro