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Searched refs:PLLE_BASE_PLDIV_CML (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c660 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) macro
736 value &= ~PLLE_BASE_PLDIV_CML(0x0f); in tegra_plle_enable()
737 value |= PLLE_BASE_PLDIV_CML(cpcon); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c945 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) macro
994 value &= ~PLLE_BASE_PLDIV_CML(0xf); in tegra_plle_enable()
997 value |= PLLE_BASE_PLDIV_CML(cpcon); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c1130 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24) macro
1183 value &= ~PLLE_BASE_PLDIV_CML(0x1f); in tegra_plle_enable()
1186 value |= PLLE_BASE_PLDIV_CML(0xe); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c631 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) macro