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Searched refs:PLLE_SS_CNTL_SSCINCINTR (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c933 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) macro
1015 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); in tegra_plle_enable()
1019 value |= PLLE_SS_CNTL_SSCINCINTR(0x20); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c1119 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) macro
1222 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); in tegra_plle_enable()
1223 value |= PLLE_SS_CNTL_SSCINCINTR(0x23); in tegra_plle_enable()