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Searched refs:PLLE_SS_CNTL_SSCMAX (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c626 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) macro
745 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); in tegra_plle_enable()
746 value |= PLLE_SS_CNTL_SSCMAX(0x24); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c655 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) macro
791 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); in tegra_plle_enable()
792 value |= PLLE_SS_CNTL_SSCMAX(0x24); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c940 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) macro
1017 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); in tegra_plle_enable()
1021 value |= PLLE_SS_CNTL_SSCMAX(0x25); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c1126 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) macro
1224 value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff); in tegra_plle_enable()
1225 value |= PLLE_SS_CNTL_SSCMAX(0x21); in tegra_plle_enable()