| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rk3368.c | 43 #define PLL_DIVISORS(hz, _nr, _no) { \ macro
50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
51 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk()
289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk()
290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
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| D | clk_rk3328.c | 32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ macro
37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
38 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
40 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
41 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
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| D | clk_rk3036.c | 31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ macro
41 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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| D | clk_rk3399.c | 44 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ macro
50 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
51 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
53 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
56 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
57 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
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| D | clk_rk322x.c | 28 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ macro
38 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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| D | clk_rk3128.c | 29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ macro
35 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
36 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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| D | clk_rk3188.c | 73 #define PLL_DIVISORS(hz, _nr, _no) {\ macro
81 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
82 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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| D | clk_rk3288.c | 132 #define PLL_DIVISORS(hz, _nr, _no) {\ macro
139 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
140 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
141 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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| D | clk_rv1108.c | 29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ macro
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