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Searched refs:PLL_POSTDIV1_SHIFT (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rk3036.h70 PLL_POSTDIV1_SHIFT = 12, enumerator
71 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
Dcru_rk322x.h72 PLL_POSTDIV1_SHIFT = 12, enumerator
73 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
Dcru_rk3128.h73 PLL_POSTDIV1_SHIFT = 12, enumerator
74 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
/external/u-boot/drivers/clk/rockchip/
Dclk_rk3036.c66 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
198 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
Dclk_rk3328.c50 PLL_POSTDIV1_SHIFT = 12, enumerator
51 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
265 (div->postdiv1 << PLL_POSTDIV1_SHIFT)); in rkclk_set_pll()
Dclk_rk322x.c64 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
199 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
Dclk_rk3128.c61 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
266 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
Dclk_rk3399.c72 PLL_POSTDIV1_SHIFT = 8, enumerator
73 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
322 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | in rkclk_set_pll()
/external/u-boot/arch/arm/mach-rockchip/rk3036/
Dsdram_rk3036.c340 (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | in rkdclk_init()